1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2021 Rockchip Electronics Co., Ltd
6 #ifndef __CONFIG_RK3568_COMMON_H
7 #define __CONFIG_RK3568_COMMON_H
9 #include "rockchip-common.h"
11 #define CONFIG_IRAM_BASE 0xfdcc0000
13 #define CONFIG_SPL_STACK 0x00400000
14 #define CONFIG_SPL_BSS_START_ADDR 0x4000000
16 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
18 #define CONFIG_SYS_SDRAM_BASE 0
19 #define SDRAM_MAX_SIZE 0xf0000000
21 #ifndef CONFIG_SPL_BUILD
22 #define ENV_MEM_LAYOUT_SETTINGS \
23 "scriptaddr=0x00c00000\0" \
24 "pxefile_addr_r=0x00e00000\0" \
25 "fdt_addr_r=0x0a100000\0" \
26 "kernel_addr_r=0x02080000\0" \
27 "ramdisk_addr_r=0x0a200000\0"
29 #include <config_distro_bootcmd.h>
30 #define CONFIG_EXTRA_ENV_SETTINGS \
31 ENV_MEM_LAYOUT_SETTINGS \
32 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
33 "partitions=" PARTS_DEFAULT \
34 ROCKCHIP_DEVICE_SETTINGS \