1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
6 #ifndef __CONFIG_RK3308_COMMON_H
7 #define __CONFIG_RK3308_COMMON_H
9 #include "rockchip-common.h"
11 #define CONFIG_SYS_CBSIZE 1024
12 #define CONFIG_SYS_MAX_NAND_DEVICE 1
13 #define CONFIG_SYS_NAND_ONFI_DETECTION
14 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
15 #define CONFIG_SYS_NAND_PAGE_COUNT 64
16 #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
17 #define CONFIG_SPL_MAX_SIZE 0x20000
18 #define CONFIG_SPL_BSS_START_ADDR 0x00400000
19 #define CONFIG_SPL_BSS_MAX_SIZE 0x2000
20 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
22 #define CONFIG_SYS_NS16550_MEM32
24 #define CONFIG_ROCKCHIP_STIMER_BASE 0xff1b00a0
25 #define CONFIG_IRAM_BASE 0xfff80000
26 #define CONFIG_SYS_INIT_SP_ADDR 0x00800000
27 #define CONFIG_SPL_STACK 0x00400000
28 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
30 #define COUNTER_FREQUENCY 24000000
32 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
34 #define CONFIG_SYS_SDRAM_BASE 0
35 #define SDRAM_MAX_SIZE 0xff000000
36 #define SDRAM_BANK_SIZE (2UL << 30)
38 #ifndef CONFIG_SPL_BUILD
40 #define ENV_MEM_LAYOUT_SETTINGS \
41 "scriptaddr=0x00500000\0" \
42 "pxefile_addr_r=0x00600000\0" \
43 "fdt_addr_r=0x02800000\0" \
44 "kernel_addr_r=0x00680000\0" \
45 "ramdisk_addr_r=0x04000000\0"
47 #include <config_distro_bootcmd.h>
48 #define CONFIG_EXTRA_ENV_SETTINGS \
49 ENV_MEM_LAYOUT_SETTINGS \
50 "partitions=" PARTS_DEFAULT \
51 ROCKCHIP_DEVICE_SETTINGS \