2 * (C) Copyright 2015 Google, Inc
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __CONFIG_RK3288_COMMON_H
8 #define __CONFIG_RK3288_COMMON_H
10 #include <asm/arch/hardware.h>
12 #define CONFIG_SYS_NO_FLASH
13 #define CONFIG_NR_DRAM_BANKS 1
14 #define CONFIG_ENV_SIZE 0x2000
15 #define CONFIG_SYS_MAXARGS 16
16 #define CONFIG_BAUDRATE 115200
17 #define CONFIG_SYS_MALLOC_LEN (32 << 20)
18 #define CONFIG_SYS_CBSIZE 1024
19 #define CONFIG_SYS_THUMB_BUILD
20 #define CONFIG_OF_LIBFDT
21 #define CONFIG_DISPLAY_BOARDINFO
23 #define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000)
24 #define CONFIG_SYS_TIMER_BASE 0xff810020 /* TIMER7 */
25 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
27 #define CONFIG_SPL_FRAMEWORK
28 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
29 #define CONFIG_SPL_LIBCOMMON_SUPPORT
30 #define CONFIG_SPL_LIBGENERIC_SUPPORT
31 #define CONFIG_SPL_SERIAL_SUPPORT
32 #define CONFIG_SYS_NS16550_MEM32
33 #define CONFIG_SPL_BOARD_INIT
35 #define CONFIG_SYS_TEXT_BASE 0x00100000
36 #define CONFIG_SYS_INIT_SP_ADDR 0x00100000
37 #define CONFIG_SYS_LOAD_ADDR 0x00800800
38 #define CONFIG_SPL_STACK 0xff718000
39 #define CONFIG_SPL_TEXT_BASE 0xff704004
41 #define CONFIG_ROCKCHIP_COMMON
42 #define CONFIG_SPL_ROCKCHIP_COMMON
44 #define CONFIG_SILENT_CONSOLE
45 #ifndef CONFIG_SPL_BUILD
46 # define CONFIG_SYS_CONSOLE_IS_IN_ENV
47 # define CONFIG_CONSOLE_MUX
52 #define CONFIG_GENERIC_MMC
53 #define CONFIG_CMD_MMC
56 #define CONFIG_BOUNCE_BUFFER
58 #define CONFIG_DOS_PARTITION
59 #define CONFIG_CMD_FAT
60 #define CONFIG_FAT_WRITE
61 #define CONFIG_CMD_EXT2
62 #define CONFIG_CMD_EXT4
63 #define CONFIG_CMD_FS_GENERIC
64 #define CONFIG_PARTITION_UUIDS
65 #define CONFIG_CMD_PART
67 /* RAW SD card / eMMC locations. */
68 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 256
69 #define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10)
71 /* FAT sd card locations. */
72 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
73 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
75 #define CONFIG_SPL_PINCTRL_SUPPORT
76 #define CONFIG_SPL_GPIO_SUPPORT
77 #define CONFIG_SPL_RAM_SUPPORT
78 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
80 #define CONFIG_CMD_CACHE
81 #define CONFIG_CMD_TIME
83 #define CONFIG_SYS_SDRAM_BASE 0
84 #define CONFIG_NR_DRAM_BANKS 1
85 #define SDRAM_BANK_SIZE (2UL << 30)
87 #define CONFIG_SPI_FLASH
90 #define CONFIG_CMD_SPI
91 #define CONFIG_SF_DEFAULT_SPEED 20000000
93 #define CONFIG_CMD_I2C
95 #ifndef CONFIG_SPL_BUILD
96 #include <config_distro_defaults.h>
98 #define ENV_MEM_LAYOUT_SETTINGS \
99 "scriptaddr=0x00000000\0" \
100 "pxefile_addr_r=0x00100000\0" \
101 "fdt_addr_r=0x01f00000\0" \
102 "kernel_addr_r=0x02000000\0" \
103 "ramdisk_addr_r=0x04000000\0"
105 /* First try to boot from SD (index 0), then eMMC (index 1 */
106 #define BOOT_TARGET_DEVICES(func) \
110 #include <config_distro_bootcmd.h>
112 /* Linux fails to load the fdt if it's loaded above 512M on a Rock 2 board, so
113 * limit the fdt reallocation to that */
114 #define CONFIG_EXTRA_ENV_SETTINGS \
115 "fdt_high=0x1fffffff\0" \
116 "initrd_high=0x1fffffff\0" \
117 ENV_MEM_LAYOUT_SETTINGS \
118 ROCKCHIP_DEVICE_SETTINGS \