2 * (C) Copyright 2015 Google, Inc
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __CONFIG_RK3188_COMMON_H
8 #define __CONFIG_RK3188_COMMON_H
10 #define CONFIG_SYS_CACHELINE_SIZE 64
12 #include <asm/arch/hardware.h>
13 #include "rockchip-common.h"
15 #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
16 #define CONFIG_NR_DRAM_BANKS 1
17 #define CONFIG_SYS_MALLOC_LEN (32 << 20)
18 #define CONFIG_SYS_CBSIZE 1024
20 #define CONFIG_SYS_NS16550_MEM32
22 #ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM
23 /* Bootrom will load u-boot binary to 0x60000000 once return from SPL */
25 #define CONFIG_SYS_INIT_SP_ADDR 0x60100000
26 #define CONFIG_SYS_LOAD_ADDR 0x60800800
28 #define CONFIG_ROCKCHIP_MAX_INIT_SIZE (0x8000 - 0x800)
29 #define CONFIG_ROCKCHIP_CHIP_TAG "RK31"
31 #define CONFIG_SPL_TEXT_BASE 0x10080800
32 /* spl size 32kb sram - 2kb bootrom */
33 #define CONFIG_SPL_MAX_SIZE (0x8000 - 0x800)
34 #define CONFIG_ROCKCHIP_SERIAL 1
36 #define CONFIG_SPL_STACK 0x10087fff
39 #define CONFIG_BOUNCE_BUFFER
41 #define CONFIG_SYS_SDRAM_BASE 0x60000000
42 #define CONFIG_NR_DRAM_BANKS 1
43 #define SDRAM_BANK_SIZE (2UL << 30)
44 #define SDRAM_MAX_SIZE 0x80000000
46 #define CONFIG_SPI_FLASH
47 #define CONFIG_SF_DEFAULT_SPEED 20000000
49 #ifndef CONFIG_SPL_BUILD
52 /* usb host support */
53 #define ENV_MEM_LAYOUT_SETTINGS \
54 "scriptaddr=0x60000000\0" \
55 "pxefile_addr_r=0x60100000\0" \
56 "fdt_addr_r=0x61f00000\0" \
57 "kernel_addr_r=0x62000000\0" \
58 "ramdisk_addr_r=0x64000000\0"
60 #include <config_distro_bootcmd.h>
62 /* Linux fails to load the fdt if it's loaded above 256M on a Rock board,
63 * so limit the fdt reallocation to that */
64 #define CONFIG_EXTRA_ENV_SETTINGS \
65 "fdt_high=0x6fffffff\0" \
66 "initrd_high=0x6fffffff\0" \
67 "partitions=" PARTS_DEFAULT \
68 ENV_MEM_LAYOUT_SETTINGS \
69 ROCKCHIP_DEVICE_SETTINGS \
72 #endif /* CONFIG_SPL_BUILD */
74 #define CONFIG_PREBOOT