include/configs/rk3188_common.h

   1 /*
   2  * (C) Copyright 2015 Google, Inc
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __CONFIG_RK3188_COMMON_H
   8 #define __CONFIG_RK3188_COMMON_H
   9
  10 #define CONFIG_SYS_CACHELINE_SIZE       64
  11
  12 #include <asm/arch/hardware.h>
  13 #include "rockchip-common.h"
  14
  15 #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
  16 #define CONFIG_NR_DRAM_BANKS            1
  17 #define CONFIG_SYS_MALLOC_LEN           (32 << 20)
  18 #define CONFIG_SYS_CBSIZE               1024
  19
  20 #define CONFIG_SYS_TIMER_RATE           (24 * 1000 * 1000)
  21 #define CONFIG_SYS_TIMER_BASE           0x2000e000 /* TIMER3 */
  22 #define CONFIG_SYS_TIMER_COUNTER        (CONFIG_SYS_TIMER_BASE + 8)
  23 #define CONFIG_SYS_TIMER_COUNTS_DOWN
  24
  25 #define CONFIG_SYS_NS16550_MEM32
  26
  27 #ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM
  28 /* Bootrom will load u-boot binary to 0x60000000 once return from SPL */
  29 #define CONFIG_SYS_TEXT_BASE            0x60000000
  30 #else
  31 #define CONFIG_SYS_TEXT_BASE            0x60100000
  32 #endif
  33 #define CONFIG_SYS_INIT_SP_ADDR         0x60100000
  34 #define CONFIG_SYS_LOAD_ADDR            0x60800800
  35
  36 #define CONFIG_ROCKCHIP_MAX_INIT_SIZE   (0x8000 - 0x800)
  37 #define CONFIG_ROCKCHIP_CHIP_TAG        "RK31"
  38
  39 #ifdef CONFIG_TPL_BUILD
  40 #define CONFIG_SPL_TEXT_BASE            0x10080804
  41 /* tpl size 1kb - 4byte RK31 header */
  42 #define CONFIG_SPL_MAX_SIZE             (0x400 - 0x4)
  43 #elif defined(CONFIG_SPL_BUILD)
  44 /* spl size 32kb sram - 2kb bootrom - 1kb spl */
  45 #define CONFIG_SPL_MAX_SIZE             (0x8000 - 0xC00)
  46 #define CONFIG_SPL_TEXT_BASE            0x10080C00
  47 #define CONFIG_SPL_FRAMEWORK            1
  48 #define CONFIG_SPL_CLK                  1
  49 #define CONFIG_SPL_PINCTRL              1
  50 #define CONFIG_SPL_REGMAP               1
  51 #define CONFIG_SPL_SYSCON               1
  52 #define CONFIG_SPL_RAM                  1
  53 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 1
  54 #define CONFIG_ROCKCHIP_SERIAL          1
  55 #endif
  56
  57 #define CONFIG_SPL_STACK                0x10087fff
  58
  59 /* MMC/SD IP block */
  60 #define CONFIG_BOUNCE_BUFFER
  61
  62 #define CONFIG_SYS_SDRAM_BASE           0x60000000
  63 #define CONFIG_NR_DRAM_BANKS            1
  64 #define SDRAM_BANK_SIZE                 (2UL << 30)
  65 #define SDRAM_MAX_SIZE                  0x80000000
  66
  67 #define CONFIG_SPI_FLASH
  68 #define CONFIG_SPI
  69 #define CONFIG_SF_DEFAULT_SPEED 20000000
  70
  71 #ifndef CONFIG_SPL_BUILD
  72 /* usb otg */
  73 #define CONFIG_ROCKCHIP_USB2_PHY
  74
  75 /* usb host support */
  76 #define ENV_MEM_LAYOUT_SETTINGS \
  77         "scriptaddr=0x60000000\0" \
  78         "pxefile_addr_r=0x60100000\0" \
  79         "fdt_addr_r=0x61f00000\0" \
  80         "kernel_addr_r=0x62000000\0" \
  81         "ramdisk_addr_r=0x64000000\0"
  82
  83 #include <config_distro_bootcmd.h>
  84
  85 /* Linux fails to load the fdt if it's loaded above 256M on a Rock board,
  86  * so limit the fdt reallocation to that */
  87 #define CONFIG_EXTRA_ENV_SETTINGS \
  88         "fdt_high=0x6fffffff\0" \
  89         "initrd_high=0x6fffffff\0" \
  90         "partitions=" PARTS_DEFAULT \
  91         ENV_MEM_LAYOUT_SETTINGS \
  92         ROCKCHIP_DEVICE_SETTINGS \
  93         BOOTENV
  94
  95 #endif /* CONFIG_SPL_BUILD */
  96
  97 #define CONFIG_PREBOOT
  98
  99 #endif