2 * Configuration for AMCC 460SX Ref (redwood)
5 * Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 /*-----------------------------------------------------------------------
29 * High Level Configuration Options
30 *----------------------------------------------------------------------*/
31 #define CONFIG_4xx 1 /* ... PPC4xx family */
32 #define CONFIG_440 1 /* ... PPC460 family */
33 #define CONFIG_460SX 1 /* ... PPC460 family */
34 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
36 /*-----------------------------------------------------------------------
37 * Include common defines/options for all AMCC boards
38 *----------------------------------------------------------------------*/
39 #define CONFIG_HOSTNAME redwood
41 #include "amcc-common.h"
43 #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
45 /*-----------------------------------------------------------------------
46 * Base addresses -- Note these are effective addresses where the
47 * actual resources get mapped (not physical addresses)
48 *----------------------------------------------------------------------*/
49 #define CONFIG_SYS_FLASH_BASE 0xfff00000 /* start of FLASH */
50 #define CONFIG_SYS_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */
51 #define CONFIG_SYS_ISRAM_BASE 0x90000000 /* internal SRAM */
53 #define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
55 #define CONFIG_SYS_PCIE_MEMBASE 0x90000000 /* mapped PCIe memory */
56 #define CONFIG_SYS_PCIE0_MEMBASE 0x90000000 /* mapped PCIe memory */
57 #define CONFIG_SYS_PCIE1_MEMBASE 0xa0000000 /* mapped PCIe memory */
58 #define CONFIG_SYS_PCIE_MEMSIZE 0x01000000
60 #define CONFIG_SYS_PCIE0_XCFGBASE 0xb0000000
61 #define CONFIG_SYS_PCIE1_XCFGBASE 0xb2000000
62 #define CONFIG_SYS_PCIE2_XCFGBASE 0xb4000000
63 #define CONFIG_SYS_PCIE0_CFGBASE 0xb6000000
64 #define CONFIG_SYS_PCIE1_CFGBASE 0xb8000000
65 #define CONFIG_SYS_PCIE2_CFGBASE 0xba000000
67 /* PCIe mapped UTL registers */
68 #define CONFIG_SYS_PCIE0_REGBASE 0xd0000000
69 #define CONFIG_SYS_PCIE1_REGBASE 0xd0010000
70 #define CONFIG_SYS_PCIE2_REGBASE 0xd0020000
72 /* System RAM mapped to PCI space */
73 #define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
74 #define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
75 #define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
77 #define CONFIG_SYS_FPGA_BASE 0xe2000000 /* epld */
78 #define CONFIG_SYS_OPER_FLASH 0xe7000000 /* SRAM - OPER Flash */
80 /*-----------------------------------------------------------------------
81 * Initial RAM & stack pointer (placed in internal SRAM)
82 *----------------------------------------------------------------------*/
83 #define CONFIG_SYS_TEMP_STACK_OCM 1
84 #define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
85 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
86 #define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
87 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
89 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
90 #define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
91 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR
93 /*-----------------------------------------------------------------------
95 *----------------------------------------------------------------------*/
96 #define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
97 #define CONFIG_DDR_ECC 1 /* with ECC support */
99 #define CONFIG_SYS_SPD_MAX_DIMMS 2
101 /* SPD i2c spd addresses */
102 #define SPD_EEPROM_ADDRESS {IIC0_DIMM0_ADDR, IIC0_DIMM1_ADDR}
103 #define IIC0_DIMM0_ADDR 0x53
104 #define IIC0_DIMM1_ADDR 0x52
106 /*-----------------------------------------------------------------------
108 *----------------------------------------------------------------------*/
109 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */
111 #define IIC0_BOOTPROM_ADDR 0x50
112 #define IIC0_ALT_BOOTPROM_ADDR 0x54
114 /* Don't probe these addrs */
115 #define CONFIG_SYS_I2C_NOPROBES {0x50, 0x52, 0x53, 0x54}
117 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
119 /*-----------------------------------------------------------------------
121 *----------------------------------------------------------------------*/
122 #undef CONFIG_ENV_IS_IN_NVRAM /* ... not in NVRAM */
123 #define CONFIG_ENV_IS_IN_FLASH 1 /* Environment uses flash */
124 #undef CONFIG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
126 #define CONFIG_PREBOOT "echo;" \
127 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
130 #undef CONFIG_BOOTARGS
132 #define CONFIG_EXTRA_ENV_SETTINGS \
133 CONFIG_AMCC_DEF_ENV \
134 CONFIG_AMCC_DEF_ENV_POWERPC \
135 CONFIG_AMCC_DEF_ENV_NOR_UPD \
136 CONFIG_AMCC_DEF_ENV_NAND_UPD \
137 "kernel_addr=fc000000\0" \
138 "fdt_addr=fc1e0000\0" \
139 "ramdisk_addr=fc200000\0" \
142 /*----------------------------------------------------------------------------+
143 | Commands in addition to amcc-common.h
144 +----------------------------------------------------------------------------*/
145 #define CONFIG_CMD_SDRAM
147 #define CONFIG_BOOTCOMMAND "run flash_self"
149 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
151 #define CONFIG_IBM_EMAC4_V4 1
152 #define CONFIG_PHY_RESET 1 /* reset phy upon startup */
153 #define CONFIG_PHY_RESET_DELAY 1000
154 #define CONFIG_M88E1141_PHY 1 /* Enable phy */
155 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
157 #define CONFIG_HAS_ETH0
158 #define CONFIG_HAS_ETH1
159 #define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
160 #define CONFIG_PHY1_ADDR 1 /* PHY address, See schematics */
162 #undef CONFIG_WATCHDOG /* watchdog disabled */
164 /*-----------------------------------------------------------------------
166 *----------------------------------------------------------------------*/
167 #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
168 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
169 #define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD (Spansion) reset cmd */
171 #define CONFIG_SYS_MAX_FLASH_BANKS 3 /* number of banks */
172 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
174 #undef CONFIG_SYS_FLASH_CHECKSUM
175 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
176 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
178 #ifdef CONFIG_ENV_IS_IN_FLASH
179 #define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
180 #define CONFIG_ENV_ADDR 0xfffa0000
181 #define CONFIG_ENV_SIZE 0x10000 /* Size of Environment vars */
182 #endif /* CONFIG_ENV_IS_IN_FLASH */
184 /*---------------------------------------------------------------------------*/
186 #endif /* __CONFIG_H */