4 #define CONFIG_CPU_SH7751 1
5 #define __LITTLE_ENDIAN__ 1
8 #define CONFIG_CONS_SCIF1 1
11 #define CONFIG_SYS_SDRAM_BASE 0x8C000000
12 #define CONFIG_SYS_SDRAM_SIZE 0x04000000
14 #define CONFIG_SYS_PBSIZE 256
16 /* Address of u-boot image in Flash */
17 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
18 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)
19 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
22 * NOR Flash ( Spantion S29GL256P )
24 #define CONFIG_SYS_FLASH_BASE (0xA0000000)
25 #define CONFIG_SYS_MAX_FLASH_BANKS (1)
26 #define CONFIG_SYS_MAX_FLASH_SECT 256
27 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
30 * SuperH Clock setting
32 #define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */
37 #define CONFIG_IDE_RESET 1
38 #define CONFIG_SYS_PIO_MODE 1
39 #define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */
40 #define CONFIG_SYS_IDE_MAXDEVICE 1
41 #define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000
42 #define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */
43 #define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */
44 #define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */
45 #define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */
48 * SuperH PCI Bridge Configration
50 #define CONFIG_SH7751_PCI
52 #endif /* __CONFIG_H */