2 * Copyright (C) 2009, Ilya Yanok, Emcraft Systems, <yanok@emcraft.com>
4 * Configuration settings for the Dave/DENX QongEVB-LITE board.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/arch/imx-regs.h>
27 /* High Level Configuration Options */
28 #define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
29 #define CONFIG_MX31 1 /* in a mx31 */
31 #define CONFIG_MX31_HCLK_FREQ 26000000 /* 26MHz */
32 #define CONFIG_MX31_CLK32 32768
34 #define CONFIG_DISPLAY_CPUINFO
35 #define CONFIG_DISPLAY_BOARDINFO
37 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
38 #define CONFIG_SETUP_MEMORY_TAGS 1
39 #define CONFIG_INITRD_TAG 1
42 * Size of malloc() pool
44 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
50 #define CONFIG_MXC_UART 1
51 #define CONFIG_SYS_MX31_UART1 1
53 #define CONFIG_MXC_GPIO
54 #define CONFIG_HW_WATCHDOG
56 #define CONFIG_MXC_SPI
57 #define CONFIG_DEFAULT_SPI_BUS 1
58 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
59 #define CONFIG_RTC_MC13783
61 #define CONFIG_FSL_PMIC
62 #define CONFIG_FSL_PMIC_BUS 1
63 #define CONFIG_FSL_PMIC_CS 0
64 #define CONFIG_FSL_PMIC_CLK 100000
65 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
69 #define CONFIG_QONG_FPGA 1
70 #define CONFIG_FPGA_BASE (CS1_BASE)
71 #define CONFIG_FPGA_LATTICE
72 #define CONFIG_FPGA_COUNT 1
74 #ifdef CONFIG_QONG_FPGA
77 #define CONFIG_DNET_BASE (CS1_BASE + QONG_FPGA_PERIPH_SIZE)
78 #define CONFIG_NET_MULTI 1
80 /* Framebuffer and LCD */
82 #define CONFIG_VIDEO_MX3
83 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
84 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
85 #define LCD_BPP LCD_COLOR16
86 #define CONFIG_SPLASH_SCREEN
87 #define CONFIG_CMD_BMP
88 #define CONFIG_BMP_16BPP
89 #define CONFIG_DISPLAY_COM57H5M10XRC
92 #define CONFIG_CMD_USB
94 #define CONFIG_USB_EHCI /* Enable EHCI USB support */
95 #define CONFIG_USB_EHCI_MXC
96 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
97 #define CONFIG_MXC_USB_PORT 2
98 #define CONFIG_MXC_USB_PORTSC (MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT)
99 #define CONFIG_MXC_USB_FLAGS MXC_EHCI_POWER_PINS_ENABLED
100 #define CONFIG_EHCI_IS_TDI
101 #define CONFIG_USB_STORAGE
102 #define CONFIG_DOS_PARTITION
103 #define CONFIG_SUPPORT_VFAT
104 #define CONFIG_CMD_EXT2
105 #define CONFIG_CMD_FAT
106 #endif /* CONFIG_CMD_USB */
109 * Reducing the ARP timeout from default 5 seconds to 200ms we speed up the
110 * initial TFTP transfer, should the user wish one, significantly.
112 #define CONFIG_ARP_TIMEOUT 200UL
114 #endif /* CONFIG_QONG_FPGA */
116 #define CONFIG_CONS_INDEX 1
117 #define CONFIG_BAUDRATE 115200
118 #define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
120 /***********************************************************
122 ***********************************************************/
124 #include <config_cmd_default.h>
126 #define CONFIG_CMD_CACHE
127 #define CONFIG_CMD_DATE
128 #define CONFIG_CMD_DHCP
129 #define CONFIG_CMD_MII
130 #define CONFIG_CMD_NAND
131 #define CONFIG_CMD_NET
132 #define CONFIG_CMD_PING
133 #define CONFIG_CMD_SETEXPR
134 #define CONFIG_CMD_SPI
136 #define BOARD_LATE_INIT
138 #define CONFIG_BOOTDELAY 5
140 #define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
142 #define xstr(s) str(s)
145 #define CONFIG_EXTRA_ENV_SETTINGS \
147 "nfsargs=setenv bootargs root=/dev/nfs rw " \
148 "nfsroot=${serverip}:${rootpath}\0" \
149 "ramargs=setenv bootargs root=/dev/ram rw\0" \
150 "addip=setenv bootargs ${bootargs} " \
151 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
152 ":${hostname}:${netdev}:off panic=1\0" \
153 "addtty=setenv bootargs ${bootargs}" \
154 " console=ttymxc0,${baudrate}\0" \
155 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
156 "addmisc=setenv bootargs ${bootargs}\0" \
157 "uboot_addr=A0000000\0" \
158 "kernel_addr=A00C0000\0" \
159 "ramdisk_addr=A0300000\0" \
160 "u-boot=qong/u-boot.bin\0" \
161 "kernel_addr_r=80800000\0" \
163 "bootfile=qong/uImage\0" \
164 "rootpath=/opt/eldk-4.2-arm/armVFP\0" \
165 "flash_self=run ramargs addip addtty addmtd addmisc;" \
166 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
167 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
168 "bootm ${kernel_addr}\0" \
169 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
170 "run nfsargs addip addtty addmtd addmisc;" \
172 "bootcmd=run flash_self\0" \
173 "load=tftp ${loadaddr} ${u-boot}\0" \
174 "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) \
175 " +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE) \
176 " +${filesize};cp.b ${fileaddr} " \
177 xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
178 "upd=run load update\0" \
181 * Miscellaneous configurable options
183 #define CONFIG_SYS_LONGHELP /* undef to save memory */
184 #define CONFIG_SYS_PROMPT "=> "
185 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
186 /* Print Buffer Size */
187 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
188 sizeof(CONFIG_SYS_PROMPT) + 16)
189 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */
190 /* Boot Argument Buffer Size */
191 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
193 /* memtest works on first 255MB of RAM */
194 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
195 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0xff000000)
197 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
199 #define CONFIG_SYS_HZ 1000
201 #define CONFIG_CMDLINE_EDITING 1
202 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
203 #ifdef CONFIG_SYS_HUSH_PARSER
204 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
207 #define CONFIG_MISC_INIT_R 1
208 /*-----------------------------------------------------------------------
211 * The stack sizes are set up in start.S using the settings below
213 #define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
215 /*-----------------------------------------------------------------------
216 * Physical Memory Map
218 #define CONFIG_NR_DRAM_BANKS 1
219 #define PHYS_SDRAM_1 CSD0_BASE
220 #define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */
227 extern void qong_nand_plat_init(void *chip);
228 extern int qong_nand_rdy(void *chip);
230 #define CONFIG_NAND_PLAT
231 #define CONFIG_SYS_MAX_NAND_DEVICE 1
232 #define CONFIG_SYS_NAND_BASE CS3_BASE
233 #define NAND_PLAT_INIT() qong_nand_plat_init(nand)
235 #define QONG_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 24))
236 #define QONG_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 23))
237 #define QONG_NAND_WRITE(addr, cmd) \
239 __REG8(addr) = cmd; \
242 #define NAND_PLAT_WRITE_CMD(chip, cmd) QONG_NAND_WRITE(QONG_NAND_CLE(chip), cmd)
243 #define NAND_PLAT_WRITE_ADR(chip, cmd) QONG_NAND_WRITE(QONG_NAND_ALE(chip), cmd)
244 #define NAND_PLAT_DEV_READY(chip) (qong_nand_rdy(chip))
246 /*-----------------------------------------------------------------------
247 * FLASH and environment organization
249 #define CONFIG_SYS_FLASH_BASE CS0_BASE
250 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
251 /* max number of sectors on one chip */
252 #define CONFIG_SYS_MAX_FLASH_SECT 1024
253 /* Monitor at beginning of flash */
254 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
255 #define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256KiB */
257 #define CONFIG_ENV_IS_IN_FLASH 1
258 #define CONFIG_ENV_SECT_SIZE 0x20000
259 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
260 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x80000)
262 /* Address and size of Redundant Environment Sector */
263 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
264 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
266 /*-----------------------------------------------------------------------
267 * CFI FLASH driver setup
269 /* Flash memory is CFI compliant */
270 #define CONFIG_SYS_FLASH_CFI 1
271 /* Use drivers/cfi_flash.c */
272 #define CONFIG_FLASH_CFI_DRIVER 1
273 /* Use buffered writes (~10x faster) */
274 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
275 /* Use hardware sector protection */
276 #define CONFIG_SYS_FLASH_PROTECTION 1
281 #define CONFIG_CMD_JFFS2
282 #define CONFIG_CMD_UBI
283 #define CONFIG_CMD_UBIFS
284 #define CONFIG_RBTREE
285 #define CONFIG_MTD_PARTITIONS
286 #define CONFIG_CMD_MTDPARTS
288 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
289 #define CONFIG_FLASH_CFI_MTD
290 #define MTDIDS_DEFAULT "nor0=physmap-flash.0," \
292 #define MTDPARTS_DEFAULT \
293 "mtdparts=physmap-flash.0:" \
294 "512k(U-Boot),128k(env1),128k(env2)," \
295 "2304k(kernel),13m(ramdisk),-(user);" \
299 /* additions for new relocation code, must be added to all boards */
300 #define CONFIG_SYS_SDRAM_BASE 0x80000000
301 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
302 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
303 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
304 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)
306 #define CONFIG_BOARD_EARLY_INIT_F 1
308 #endif /* __CONFIG_H */