3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
9 * Copied from lubbock.h
12 * BEC Systems <http://bec-systems.com>
13 * Cliff Brake <cliff.brake@gmail.com>
14 * Configuation settings for the Accelent/Vibren PXA255 IDP
16 * See file CREDITS for list of people who contributed to this
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License as
21 * published by the Free Software Foundation; either version 2 of
22 * the License, or (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
38 #include <asm/arch/pxa-regs.h>
41 * If we are developing, we might want to start U-Boot from RAM
42 * so we MUST NOT initialize critical regs like mem-timing ...
44 #undef CONFIG_SKIP_LOWLEVEL_INIT /* define for developing */
45 #undef CONFIG_SKIP_RELOCATE_UBOOT /* define for developing */
46 #define CONFIG_SYS_TEXT_BASE 0x0
49 * define the following to enable debug blinks. A debug blink function
50 * must be defined in memsetup.S
52 #undef DEBUG_BLINK_ENABLE
53 #undef DEBUG_BLINKC_ENABLE
56 * High Level Configuration Options
59 #define CONFIG_PXA250 1 /* This is an PXA250 CPU */
63 #define CONFIG_SHARP_LM8V31
67 #define CONFIG_DOS_PARTITION 1
68 #define BOARD_LATE_INIT 1
70 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
72 /* we will never enable dcache, because we have to setup MMU first */
73 #define CONFIG_SYS_NO_DCACHE
76 * Size of malloc() pool
78 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
79 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
82 * PXA250 IDP memory map information
85 #define IDP_CS5_ETH_OFFSET 0x03400000
91 #define CONFIG_NET_MULTI
92 #define CONFIG_SMC91111
93 #define CONFIG_SMC91111_BASE (PXA_CS5_PHYS + IDP_CS5_ETH_OFFSET + 0x300)
94 #define CONFIG_SMC_USE_32_BIT 1
95 /* #define CONFIG_SMC_USE_IOFUNCS */
97 /* the following has to be set high -- suspect something is wrong with
98 * with the tftp timeout routines. FIXME!!!
100 #define CONFIG_NET_RETRY_COUNT 100
103 * select serial console configuration
105 #define CONFIG_PXA_SERIAL
106 #define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */
108 /* allow to overwrite serial and ethaddr */
109 #define CONFIG_ENV_OVERWRITE
111 #define CONFIG_BAUDRATE 115200
117 #define CONFIG_BOOTP_BOOTFILESIZE
118 #define CONFIG_BOOTP_BOOTPATH
119 #define CONFIG_BOOTP_GATEWAY
120 #define CONFIG_BOOTP_HOSTNAME
124 * Command line configuration.
126 #include <config_cmd_default.h>
128 #define CONFIG_CMD_FAT
129 #define CONFIG_CMD_DHCP
131 #define CONFIG_BOOTDELAY 3
132 #define CONFIG_BOOTCOMMAND "bootm 40000"
133 #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
135 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
136 #define CONFIG_SETUP_MEMORY_TAGS 1
137 /* #define CONFIG_INITRD_TAG 1 */
140 * Current memory map for Vibren supplied Linux images:
143 * 0 - 0x3ffff (size = 0x40000): bootloader
144 * 0x40000 - 0x13ffff (size = 0x100000): kernel
145 * 0x140000 - 0x1f3ffff (size = 0x1e00000): jffs
148 * 0xa0008000 - kernel is loaded
149 * 0xa3000000 - Uboot runs (48MB into RAM)
153 #define CONFIG_EXTRA_ENV_SETTINGS \
155 "mw.b 0xa0000000 0xff 0x40000; " \
157 "fatload mmc 0 0xa0000000 u-boot.bin; " \
159 "protect off 0x0 0x3ffff; " \
160 "erase 0x0 0x3ffff; " \
161 "cp.b 0xa0000000 0x0 0x40000; " \
164 "prog_uzImage_mmc=" \
165 "mw.b 0xa0000000 0xff 0x100000; " \
167 "fatload mmc 0 0xa0000000 uzImage; " \
169 "protect off 0x40000 0xfffff; " \
170 "erase 0x40000 0xfffff; " \
171 "cp.b 0xa0000000 0x40000 0x100000; " \
174 "mw.b 0xa0000000 0xff 0x1e00000; " \
176 "fatload mmc 0 0xa0000000 root.jffs; " \
178 "protect off 0x140000 0x1f3ffff; " \
179 "erase 0x140000 0x1f3ffff; " \
180 "cp.b 0xa0000000 0x140000 0x1e00000; " \
184 "fatload mmc 0 0xa1000000 uzImage && " \
186 "bootm 0xa1000000; " \
189 "mw.b 0xa0000000 0xff 0x100000; " \
190 "if bootp 0xa0000000 u-boot.bin; " \
192 "protect off 0x0 0x3ffff; " \
193 "erase 0x0 0x3ffff; " \
194 "cp.b 0xa0000000 0x0 0x40000; " \
197 "prog_uzImage_net=" \
198 "mw.b 0xa0000000 0xff 0x100000; " \
199 "if bootp 0xa0000000 uzImage; " \
201 "protect off 0x40000 0xfffff; " \
202 "erase 0x40000 0xfffff; " \
203 "cp.b 0xa0000000 0x40000 0x100000; " \
206 "mw.b 0xa0000000 0xff 0x1e00000; " \
207 "if bootp 0xa0000000 root.jffs; " \
209 "protect off 0x140000 0x1f3ffff; " \
210 "erase 0x140000 0x1f3ffff; " \
211 "cp.b 0xa0000000 0x140000 0x1e00000; " \
219 #if defined(CONFIG_CMD_KGDB)
220 #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
221 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
225 * Miscellaneous configurable options
227 #define CONFIG_SYS_HUSH_PARSER 1
228 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
230 #define CONFIG_SYS_LONGHELP /* undef to save memory */
231 #ifdef CONFIG_SYS_HUSH_PARSER
232 #define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */
234 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
236 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
237 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
238 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
239 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
240 #define CONFIG_SYS_DEVICE_NULLDEV 1
242 #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
243 #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
245 #define CONFIG_SYS_LOAD_ADDR 0xa0800000 /* default load address */
247 #define CONFIG_SYS_HZ 1000
248 #define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
250 #define RTC 1 /* enable 32KHz osc */
252 /* valid baudrates */
253 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
256 #define CONFIG_PXA_MMC
257 #define CONFIG_CMD_MMC
258 #define CONFIG_SYS_MMC_BASE 0xF0000000
264 * The stack sizes are set up in start.S using the settings below
266 #define CONFIG_STACKSIZE (128*1024) /* regular stack */
267 #ifdef CONFIG_USE_IRQ
268 #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
269 #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
273 * Physical Memory Map
275 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
276 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
277 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
278 #define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
279 #define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
280 #define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
281 #define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
282 #define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
283 #define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
285 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
286 #define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
287 #define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
288 #define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */
289 #define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
291 #define CONFIG_SYS_DRAM_BASE 0xa0000000
292 #define CONFIG_SYS_DRAM_SIZE 0x04000000
294 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
296 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
297 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
303 #define CONFIG_SYS_GAFR0_L_VAL 0x80001005
304 #define CONFIG_SYS_GAFR0_U_VAL 0xa5128012
305 #define CONFIG_SYS_GAFR1_L_VAL 0x699a9558
306 #define CONFIG_SYS_GAFR1_U_VAL 0xaaa5aa6a
307 #define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
308 #define CONFIG_SYS_GAFR2_U_VAL 0x2
309 #define CONFIG_SYS_GPCR0_VAL 0x1800400
310 #define CONFIG_SYS_GPCR1_VAL 0x0
311 #define CONFIG_SYS_GPCR2_VAL 0x0
312 #define CONFIG_SYS_GPDR0_VAL 0xc1818440
313 #define CONFIG_SYS_GPDR1_VAL 0xfcffab82
314 #define CONFIG_SYS_GPDR2_VAL 0x1ffff
315 #define CONFIG_SYS_GPSR0_VAL 0x8000
316 #define CONFIG_SYS_GPSR1_VAL 0x3f0002
317 #define CONFIG_SYS_GPSR2_VAL 0x1c000
319 #define CONFIG_SYS_PSSR_VAL 0x20
321 #define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10
322 #define CONFIG_SYS_CKEN 0x0
327 #define CONFIG_SYS_MSC0_VAL 0x29DCA4D2
328 #define CONFIG_SYS_MSC1_VAL 0x43AC494C
329 #define CONFIG_SYS_MSC2_VAL 0x39D449D4
330 #define CONFIG_SYS_MDCNFG_VAL 0x090009C9
331 #define CONFIG_SYS_MDREFR_VAL 0x0085C017
332 #define CONFIG_SYS_MDMRS_VAL 0x00220022
333 #define CONFIG_SYS_FLYCNFG_VAL 0x00000000
334 #define CONFIG_SYS_SXCNFG_VAL 0x00000000
337 * PCMCIA and CF Interfaces
339 #define CONFIG_SYS_MECR_VAL 0x00000003
340 #define CONFIG_SYS_MCMEM0_VAL 0x00014405
341 #define CONFIG_SYS_MCMEM1_VAL 0x00014405
342 #define CONFIG_SYS_MCATT0_VAL 0x00014405
343 #define CONFIG_SYS_MCATT1_VAL 0x00014405
344 #define CONFIG_SYS_MCIO0_VAL 0x00014405
345 #define CONFIG_SYS_MCIO1_VAL 0x00014405
348 * FLASH and environment organization
350 #define CONFIG_SYS_FLASH_CFI
351 #define CONFIG_FLASH_CFI_DRIVER 1
353 #define CONFIG_SYS_MONITOR_BASE 0
354 #define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE
356 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
357 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
359 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
361 /* timeout values are in ticks */
362 #define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
363 #define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */
365 /* put cfg at end of flash for now */
366 #define CONFIG_ENV_IS_IN_FLASH 1
367 /* Addr of Environment Sector */
368 #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SIZE - 0x40000)
369 #define CONFIG_ENV_SIZE PHYS_FLASH_SECT_SIZE /* Total Size of Environment Sector */
370 #define CONFIG_ENV_SECT_SIZE (PHYS_FLASH_SECT_SIZE / 16)
372 #endif /* __CONFIG_H */