include/configs/pxa255_idp.h

   1 /*
   2  * (C) Copyright 2002
   3  * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
   4  *
   5  * (C) Copyright 2002
   6  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   7  * Marius Groeger <mgroeger@sysgo.de>
   8  *
   9  * Copied from lubbock.h
  10  *
  11  * (C) Copyright 2004
  12  * BEC Systems <http://bec-systems.com>
  13  * Cliff Brake <cliff.brake@gmail.com>
  14  * Configuation settings for the Accelent/Vibren PXA255 IDP
  15  *
  16  * See file CREDITS for list of people who contributed to this
  17  * project.
  18  *
  19  * This program is free software; you can redistribute it and/or
  20  * modify it under the terms of the GNU General Public License as
  21  * published by the Free Software Foundation; either version 2 of
  22  * the License, or (at your option) any later version.
  23  *
  24  * This program is distributed in the hope that it will be useful,
  25  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  27  * GNU General Public License for more details.
  28  *
  29  * You should have received a copy of the GNU General Public License
  30  * along with this program; if not, write to the Free Software
  31  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  32  * MA 02111-1307 USA
  33  */
  34
  35 #ifndef __CONFIG_H
  36 #define __CONFIG_H
  37
  38 #include <asm/arch/pxa-regs.h>
  39
  40 /*
  41  * If we are developing, we might want to start armboot from ram
  42  * so we MUST NOT initialize critical regs like mem-timing ...
  43  */
  44 #define CONFIG_INIT_CRITICAL                    /* undef for developing */
  45
  46 /*
  47  * define the following to enable debug blinks.  A debug blink function
  48  * must be defined in memsetup.S
  49  */
  50 #undef DEBUG_BLINK_ENABLE
  51 #undef DEBUG_BLINKC_ENABLE
  52
  53 /*
  54  * High Level Configuration Options
  55  * (easy to change)
  56  */
  57 #define CONFIG_PXA250           1       /* This is an PXA250 CPU    */
  58
  59 #undef CONFIG_LCD
  60 #ifdef CONFIG_LCD
  61 #define CONFIG_SHARP_LM8V31
  62 #endif
  63
  64 #define CONFIG_MMC              1
  65 #define BOARD_LATE_INIT         1
  66
  67 #undef CONFIG_USE_IRQ                   /* we don't need IRQ/FIQ stuff */
  68
  69 /*
  70  * Size of malloc() pool
  71  */
  72 #define CFG_MALLOC_LEN      (CFG_ENV_SIZE + 128*1024)
  73 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
  74
  75 /*
  76  * PXA250 IDP memory map information
  77  */
  78
  79 #define IDP_CS5_ETH_OFFSET      0x03400000
  80
  81
  82 /*
  83  * Hardware drivers
  84  */
  85 #define CONFIG_DRIVER_SMC91111
  86 #define CONFIG_SMC91111_BASE    (PXA_CS5_PHYS + IDP_CS5_ETH_OFFSET + 0x300)
  87 #define CONFIG_SMC_USE_32_BIT   1
  88 /* #define CONFIG_SMC_USE_IOFUNCS */
  89
  90 /* the following has to be set high -- suspect something is wrong with
  91  * with the tftp timeout routines. FIXME!!!
  92  */
  93 #define CONFIG_NET_RETRY_COUNT  100
  94
  95 /*
  96  * select serial console configuration
  97  */
  98 #define CONFIG_FFUART          1       /* we use FFUART on LUBBOCK */
  99
 100 /* allow to overwrite serial and ethaddr */
 101 #define CONFIG_ENV_OVERWRITE
 102
 103 #define CONFIG_BAUDRATE         115200
 104
 105
 106 /*
 107  * BOOTP options
 108  */
 109 #define CONFIG_BOOTP_BOOTFILESIZE
 110 #define CONFIG_BOOTP_BOOTPATH
 111 #define CONFIG_BOOTP_GATEWAY
 112 #define CONFIG_BOOTP_HOSTNAME
 113
 114
 115 /*
 116  * Command line configuration.
 117  */
 118 #include <config_cmd_default.h>
 119
 120 #define CONFIG_CMD_MMC
 121 #define CONFIG_CMD_FAT
 122 #define CONFIG_CMD_DHCP
 123
 124
 125 #define CONFIG_BOOTDELAY        3
 126 #define CONFIG_BOOTCOMMAND      "bootm 40000"
 127 #define CONFIG_BOOTARGS         "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
 128 #define CONFIG_CMDLINE_TAG
 129
 130 /*
 131  * Current memory map for Vibren supplied Linux images:
 132  *
 133  * Flash:
 134  * 0 - 0x3ffff (size = 0x40000): bootloader
 135  * 0x40000 - 0x13ffff (size = 0x100000): kernel
 136  * 0x140000 - 0x1f3ffff (size = 0x1e00000): jffs
 137  *
 138  * RAM:
 139  * 0xa0008000 - kernel is loaded
 140  * 0xa3000000 - Uboot runs (48MB into RAM)
 141  *
 142  */
 143
 144 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 145         "prog_boot_mmc="                                                \
 146                         "mw.b 0xa0000000 0xff 0x40000; "                \
 147                         "if      mmcinit && "                           \
 148                                 "fatload mmc 0 0xa0000000 u-boot.bin; " \
 149                         "then "                                         \
 150                                 "protect off 0x0 0x3ffff; "             \
 151                                 "erase 0x0 0x3ffff; "                   \
 152                                 "cp.b 0xa0000000 0x0 0x40000; "         \
 153                                 "reset;"                                \
 154                         "fi\0"                                          \
 155         "prog_uzImage_mmc="                                             \
 156                         "mw.b 0xa0000000 0xff 0x100000; "               \
 157                         "if      mmcinit && "                           \
 158                                 "fatload mmc 0 0xa0000000 uzImage; "    \
 159                         "then "                                         \
 160                                 "protect off 0x40000 0xfffff; "         \
 161                                 "erase 0x40000 0xfffff; "               \
 162                                 "cp.b 0xa0000000 0x40000 0x100000; "    \
 163                         "fi\0"                                          \
 164         "prog_jffs_mmc="                                                \
 165                         "mw.b 0xa0000000 0xff 0x1e00000; "              \
 166                         "if      mmcinit && "                           \
 167                                 "fatload mmc 0 0xa0000000 root.jffs; "  \
 168                         "then "                                         \
 169                                 "protect off 0x140000 0x1f3ffff; "      \
 170                                 "erase 0x140000 0x1f3ffff; "            \
 171                                 "cp.b 0xa0000000 0x140000 0x1e00000; "  \
 172                         "fi\0"                                          \
 173         "boot_mmc="                                                     \
 174                         "if      mmcinit && "                           \
 175                                 "fatload mmc 0 0xa1000000 uzImage && "  \
 176                         "then "                                         \
 177                                 "bootm 0xa1000000; "                    \
 178                         "fi\0"                                          \
 179         "prog_boot_net="                                                \
 180                         "mw.b 0xa0000000 0xff 0x100000; "               \
 181                         "if      bootp 0xa0000000 u-boot.bin; "         \
 182                         "then "                                         \
 183                                 "protect off 0x0 0x3ffff; "             \
 184                                 "erase 0x0 0x3ffff; "                   \
 185                                 "cp.b 0xa0000000 0x0 0x40000; "         \
 186                                 "reset; "                               \
 187                         "fi\0"                                          \
 188         "prog_uzImage_net="                                             \
 189                         "mw.b 0xa0000000 0xff 0x100000; "               \
 190                         "if      bootp 0xa0000000 uzImage; "            \
 191                         "then "                                         \
 192                                 "protect off 0x40000 0xfffff; "         \
 193                                 "erase 0x40000 0xfffff; "               \
 194                                 "cp.b 0xa0000000 0x40000 0x100000; "    \
 195                         "fi\0"                                          \
 196         "prog_jffs_net="                                                \
 197                         "mw.b 0xa0000000 0xff 0x1e00000; "              \
 198                         "if      bootp 0xa0000000 root.jffs; "          \
 199                         "then "                                         \
 200                                 "protect off 0x140000 0x1f3ffff; "      \
 201                                 "erase 0x140000 0x1f3ffff; "            \
 202                                 "cp.b 0xa0000000 0x140000 0x1e00000; "  \
 203                         "fi\0"
 204
 205
 206 /*      "erase_env="                    */
 207 /*                      "protect off"   */
 208
 209
 210 #if defined(CONFIG_CMD_KGDB)
 211 #define CONFIG_KGDB_BAUDRATE    115200          /* speed to run kgdb serial port */
 212 #define CONFIG_KGDB_SER_INDEX   2               /* which serial port to use */
 213 #endif
 214
 215 /*
 216  * Miscellaneous configurable options
 217  */
 218 #define CFG_HUSH_PARSER         1
 219 #define CFG_PROMPT_HUSH_PS2     "> "
 220
 221 #define CFG_LONGHELP                            /* undef to save memory         */
 222 #ifdef CFG_HUSH_PARSER
 223 #define CFG_PROMPT              "$ "            /* Monitor Command Prompt */
 224 #else
 225 #define CFG_PROMPT              "=> "           /* Monitor Command Prompt */
 226 #endif
 227 #define CFG_CBSIZE              256             /* Console I/O Buffer Size      */
 228 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 229 #define CFG_MAXARGS             16              /* max number of command args   */
 230 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
 231 #define CFG_DEVICE_NULLDEV      1
 232
 233 #define CFG_MEMTEST_START       0xa0400000      /* memtest works on     */
 234 #define CFG_MEMTEST_END         0xa0800000      /* 4 ... 8 MB in DRAM   */
 235
 236 #undef  CFG_CLKS_IN_HZ          /* everything, incl board info, in Hz */
 237
 238 #define CFG_LOAD_ADDR           0xa0800000      /* default load address */
 239
 240 #define CFG_HZ                  3686400         /* incrementer freq: 3.6864 MHz */
 241 #define CFG_CPUSPEED            0x161           /* set core clock to 400/200/100 MHz */
 242
 243 #define RTC     1                               /* enable 32KHz osc */
 244
 245                                                 /* valid baudrates */
 246 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 247
 248 #define CFG_MMC_BASE            0xF0000000
 249
 250 /*
 251  * Stack sizes
 252  *
 253  * The stack sizes are set up in start.S using the settings below
 254  */
 255 #define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
 256 #ifdef CONFIG_USE_IRQ
 257 #define CONFIG_STACKSIZE_IRQ    (4*1024)        /* IRQ stack */
 258 #define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
 259 #endif
 260
 261 /*
 262  * Physical Memory Map
 263  */
 264 #define CONFIG_NR_DRAM_BANKS    4          /* we have 1 banks of DRAM */
 265 #define PHYS_SDRAM_1            0xa0000000 /* SDRAM Bank #1 */
 266 #define PHYS_SDRAM_1_SIZE       0x04000000 /* 64 MB */
 267 #define PHYS_SDRAM_2            0xa4000000 /* SDRAM Bank #2 */
 268 #define PHYS_SDRAM_2_SIZE       0x00000000 /* 0 MB */
 269 #define PHYS_SDRAM_3            0xa8000000 /* SDRAM Bank #3 */
 270 #define PHYS_SDRAM_3_SIZE       0x00000000 /* 0 MB */
 271 #define PHYS_SDRAM_4            0xac000000 /* SDRAM Bank #4 */
 272 #define PHYS_SDRAM_4_SIZE       0x00000000 /* 0 MB */
 273
 274 #define PHYS_FLASH_1            0x00000000 /* Flash Bank #1 */
 275 #define PHYS_FLASH_2            0x04000000 /* Flash Bank #2 */
 276 #define PHYS_FLASH_SIZE         0x02000000 /* 32 MB */
 277 #define PHYS_FLASH_BANK_SIZE    0x02000000 /* 32 MB Banks */
 278 #define PHYS_FLASH_SECT_SIZE    0x00040000 /* 256 KB sectors (x2) */
 279
 280 #define CFG_DRAM_BASE           0xa0000000
 281 #define CFG_DRAM_SIZE           0x04000000
 282
 283 #define CFG_FLASH_BASE          PHYS_FLASH_1
 284
 285 /*
 286  * GPIO settings
 287  */
 288
 289 #define CFG_GAFR0_L_VAL 0x80001005
 290 #define CFG_GAFR0_U_VAL 0xa5128012
 291 #define CFG_GAFR1_L_VAL 0x699a9558
 292 #define CFG_GAFR1_U_VAL 0xaaa5aa6a
 293 #define CFG_GAFR2_L_VAL 0xaaaaaaaa
 294 #define CFG_GAFR2_U_VAL 0x2
 295 #define CFG_GPCR0_VAL   0x1800400
 296 #define CFG_GPCR1_VAL   0x0
 297 #define CFG_GPCR2_VAL   0x0
 298 #define CFG_GPDR0_VAL   0xc1818440
 299 #define CFG_GPDR1_VAL   0xfcffab82
 300 #define CFG_GPDR2_VAL   0x1ffff
 301 #define CFG_GPSR0_VAL   0x8000
 302 #define CFG_GPSR1_VAL   0x3f0002
 303 #define CFG_GPSR2_VAL   0x1c000
 304
 305 #define CFG_PSSR_VAL            0x20
 306
 307 /*
 308  * Memory settings
 309  */
 310 #define CFG_MSC0_VAL            0x29DCA4D2
 311 #define CFG_MSC1_VAL            0x43AC494C
 312 #define CFG_MSC2_VAL            0x39D449D4
 313 #define CFG_MDCNFG_VAL          0x090009C9
 314 #define CFG_MDREFR_VAL          0x0085C017
 315 #define CFG_MDMRS_VAL           0x00220022
 316
 317 /*
 318  * PCMCIA and CF Interfaces
 319  */
 320 #define CFG_MECR_VAL            0x00000003
 321 #define CFG_MCMEM0_VAL          0x00014405
 322 #define CFG_MCMEM1_VAL          0x00014405
 323 #define CFG_MCATT0_VAL          0x00014405
 324 #define CFG_MCATT1_VAL          0x00014405
 325 #define CFG_MCIO0_VAL           0x00014405
 326 #define CFG_MCIO1_VAL           0x00014405
 327
 328 /*
 329  * FLASH and environment organization
 330  */
 331 #define CFG_FLASH_CFI
 332 #define CFG_FLASH_CFI_DRIVER    1
 333
 334 #define CFG_MONITOR_BASE        0
 335 #define CFG_MONITOR_LEN         0x40000
 336
 337 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 338 #define CFG_MAX_FLASH_SECT      128  /* max number of sectors on one chip    */
 339
 340 #define CFG_FLASH_USE_BUFFER_WRITE      1
 341
 342 /* timeout values are in ticks */
 343 #define CFG_FLASH_ERASE_TOUT    (25*CFG_HZ) /* Timeout for Flash Erase */
 344 #define CFG_FLASH_WRITE_TOUT    (25*CFG_HZ) /* Timeout for Flash Write */
 345
 346 /* put cfg at end of flash for now */
 347 #define CFG_ENV_IS_IN_FLASH     1
 348  /* Addr of Environment Sector  */
 349 #define CFG_ENV_ADDR            (PHYS_FLASH_1 + PHYS_FLASH_SIZE - 0x40000)
 350 #define CFG_ENV_SIZE            0x40000 /* Total Size of Environment Sector     */
 351 #define CFG_ENV_SECT_SIZE       0x40000
 352
 353 #endif  /* __CONFIG_H */