include/configs/pxa255_idp.h

   1 /*
   2  * (C) Copyright 2002
   3  * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
   4  *
   5  * (C) Copyright 2002
   6  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   7  * Marius Groeger <mgroeger@sysgo.de>
   8  *
   9  * Copied from lubbock.h
  10  *
  11  * (C) Copyright 2004
  12  * BEC Systems <http://bec-systems.com>
  13  * Cliff Brake <cliff.brake@gmail.com>
  14  * Configuation settings for the Accelent/Vibren PXA255 IDP
  15  *
  16  * SPDX-License-Identifier:     GPL-2.0+
  17  */
  18
  19 #ifndef __CONFIG_H
  20 #define __CONFIG_H
  21
  22 #include <asm/arch/pxa-regs.h>
  23
  24 /*
  25  * If we are developing, we might want to start U-Boot from RAM
  26  * so we MUST NOT initialize critical regs like mem-timing ...
  27  */
  28 #undef CONFIG_SKIP_LOWLEVEL_INIT                        /* define for developing */
  29 #define CONFIG_SYS_TEXT_BASE    0x0
  30
  31 /*
  32  * define the following to enable debug blinks.  A debug blink function
  33  * must be defined in memsetup.S
  34  */
  35 #undef DEBUG_BLINK_ENABLE
  36 #undef DEBUG_BLINKC_ENABLE
  37
  38 /*
  39  * High Level Configuration Options
  40  * (easy to change)
  41  */
  42 #define CONFIG_CPU_PXA25X               1       /* This is an PXA250 CPU    */
  43
  44 #undef CONFIG_LCD
  45 #ifdef CONFIG_LCD
  46 #define CONFIG_PXA_LCD
  47 #define CONFIG_SHARP_LM8V31
  48 #endif
  49
  50 #define CONFIG_MMC              1
  51 #define CONFIG_DOS_PARTITION    1
  52 #define CONFIG_BOARD_LATE_INIT
  53
  54 /* we will never enable dcache, because we have to setup MMU first */
  55 #define CONFIG_SYS_DCACHE_OFF
  56
  57 /*
  58  * Size of malloc() pool
  59  */
  60 #define CONFIG_SYS_MALLOC_LEN       (CONFIG_ENV_SIZE + 128*1024)
  61
  62 /*
  63  * PXA250 IDP memory map information
  64  */
  65
  66 #define IDP_CS5_ETH_OFFSET      0x03400000
  67
  68
  69 /*
  70  * Hardware drivers
  71  */
  72 #define CONFIG_SMC91111
  73 #define CONFIG_SMC91111_BASE    (PXA_CS5_PHYS + IDP_CS5_ETH_OFFSET + 0x300)
  74 #define CONFIG_SMC_USE_32_BIT   1
  75 /* #define CONFIG_SMC_USE_IOFUNCS */
  76
  77 /* the following has to be set high -- suspect something is wrong with
  78  * with the tftp timeout routines. FIXME!!!
  79  */
  80 #define CONFIG_NET_RETRY_COUNT  100
  81
  82 /*
  83  * select serial console configuration
  84  */
  85 #define CONFIG_PXA_SERIAL
  86 #define CONFIG_FFUART          1       /* we use FFUART on LUBBOCK */
  87 #define CONFIG_CONS_INDEX       3
  88
  89 /* allow to overwrite serial and ethaddr */
  90 #define CONFIG_ENV_OVERWRITE
  91
  92 #define CONFIG_BAUDRATE         115200
  93
  94
  95 /*
  96  * BOOTP options
  97  */
  98 #define CONFIG_BOOTP_BOOTFILESIZE
  99 #define CONFIG_BOOTP_BOOTPATH
 100 #define CONFIG_BOOTP_GATEWAY
 101 #define CONFIG_BOOTP_HOSTNAME
 102
 103
 104 /*
 105  * Command line configuration.
 106  */
 107 #include <config_cmd_default.h>
 108
 109 #define CONFIG_CMD_FAT
 110 #define CONFIG_CMD_DHCP
 111
 112 #define CONFIG_BOOTDELAY        3
 113 #define CONFIG_BOOTCOMMAND      "bootm 40000"
 114 #define CONFIG_BOOTARGS         "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
 115
 116 #define CONFIG_CMDLINE_TAG              1       /* enable passing of ATAGs */
 117 #define CONFIG_SETUP_MEMORY_TAGS        1
 118 /* #define CONFIG_INITRD_TAG            1 */
 119
 120 /*
 121  * Current memory map for Vibren supplied Linux images:
 122  *
 123  * Flash:
 124  * 0 - 0x3ffff (size = 0x40000): bootloader
 125  * 0x40000 - 0x13ffff (size = 0x100000): kernel
 126  * 0x140000 - 0x1f3ffff (size = 0x1e00000): jffs
 127  *
 128  * RAM:
 129  * 0xa0008000 - kernel is loaded
 130  * 0xa3000000 - Uboot runs (48MB into RAM)
 131  *
 132  */
 133
 134 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 135         "prog_boot_mmc="                                                \
 136                         "mw.b 0xa0000000 0xff 0x40000; "                \
 137                         "if      mmcinit && "                           \
 138                                 "fatload mmc 0 0xa0000000 u-boot.bin; " \
 139                         "then "                                         \
 140                                 "protect off 0x0 0x3ffff; "             \
 141                                 "erase 0x0 0x3ffff; "                   \
 142                                 "cp.b 0xa0000000 0x0 0x40000; "         \
 143                                 "reset;"                                \
 144                         "fi\0"                                          \
 145         "prog_uzImage_mmc="                                             \
 146                         "mw.b 0xa0000000 0xff 0x100000; "               \
 147                         "if      mmcinit && "                           \
 148                                 "fatload mmc 0 0xa0000000 uzImage; "    \
 149                         "then "                                         \
 150                                 "protect off 0x40000 0xfffff; "         \
 151                                 "erase 0x40000 0xfffff; "               \
 152                                 "cp.b 0xa0000000 0x40000 0x100000; "    \
 153                         "fi\0"                                          \
 154         "prog_jffs_mmc="                                                \
 155                         "mw.b 0xa0000000 0xff 0x1e00000; "              \
 156                         "if      mmcinit && "                           \
 157                                 "fatload mmc 0 0xa0000000 root.jffs; "  \
 158                         "then "                                         \
 159                                 "protect off 0x140000 0x1f3ffff; "      \
 160                                 "erase 0x140000 0x1f3ffff; "            \
 161                                 "cp.b 0xa0000000 0x140000 0x1e00000; "  \
 162                         "fi\0"                                          \
 163         "boot_mmc="                                                     \
 164                         "if      mmcinit && "                           \
 165                                 "fatload mmc 0 0xa1000000 uzImage && "  \
 166                         "then "                                         \
 167                                 "bootm 0xa1000000; "                    \
 168                         "fi\0"                                          \
 169         "prog_boot_net="                                                \
 170                         "mw.b 0xa0000000 0xff 0x100000; "               \
 171                         "if      bootp 0xa0000000 u-boot.bin; "         \
 172                         "then "                                         \
 173                                 "protect off 0x0 0x3ffff; "             \
 174                                 "erase 0x0 0x3ffff; "                   \
 175                                 "cp.b 0xa0000000 0x0 0x40000; "         \
 176                                 "reset; "                               \
 177                         "fi\0"                                          \
 178         "prog_uzImage_net="                                             \
 179                         "mw.b 0xa0000000 0xff 0x100000; "               \
 180                         "if      bootp 0xa0000000 uzImage; "            \
 181                         "then "                                         \
 182                                 "protect off 0x40000 0xfffff; "         \
 183                                 "erase 0x40000 0xfffff; "               \
 184                                 "cp.b 0xa0000000 0x40000 0x100000; "    \
 185                         "fi\0"                                          \
 186         "prog_jffs_net="                                                \
 187                         "mw.b 0xa0000000 0xff 0x1e00000; "              \
 188                         "if      bootp 0xa0000000 root.jffs; "          \
 189                         "then "                                         \
 190                                 "protect off 0x140000 0x1f3ffff; "      \
 191                                 "erase 0x140000 0x1f3ffff; "            \
 192                                 "cp.b 0xa0000000 0x140000 0x1e00000; "  \
 193                         "fi\0"
 194
 195
 196 /*      "erase_env="                    */
 197 /*                      "protect off"   */
 198
 199
 200 #if defined(CONFIG_CMD_KGDB)
 201 #define CONFIG_KGDB_BAUDRATE    115200          /* speed to run kgdb serial port */
 202 #define CONFIG_KGDB_SER_INDEX   2               /* which serial port to use */
 203 #endif
 204
 205 /*
 206  * Miscellaneous configurable options
 207  */
 208 #define CONFIG_SYS_HUSH_PARSER          1
 209
 210 #define CONFIG_SYS_LONGHELP                             /* undef to save memory         */
 211 #ifdef CONFIG_SYS_HUSH_PARSER
 212 #define CONFIG_SYS_PROMPT               "$ "            /* Monitor Command Prompt */
 213 #else
 214 #define CONFIG_SYS_PROMPT               "=> "           /* Monitor Command Prompt */
 215 #endif
 216 #define CONFIG_SYS_CBSIZE               256             /* Console I/O Buffer Size      */
 217 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 218 #define CONFIG_SYS_MAXARGS              16              /* max number of command args   */
 219 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 220 #define CONFIG_SYS_DEVICE_NULLDEV       1
 221
 222 #define CONFIG_SYS_MEMTEST_START        0xa0400000      /* memtest works on     */
 223 #define CONFIG_SYS_MEMTEST_END          0xa0800000      /* 4 ... 8 MB in DRAM   */
 224
 225 #define CONFIG_SYS_LOAD_ADDR            0xa0800000      /* default load address */
 226
 227 #define CONFIG_SYS_HZ                   1000
 228 #define CONFIG_SYS_CPUSPEED             0x161           /* set core clock to 400/200/100 MHz */
 229
 230 #define RTC     1                               /* enable 32KHz osc */
 231
 232 #ifdef CONFIG_MMC
 233 #define CONFIG_GENERIC_MMC
 234 #define CONFIG_PXA_MMC_GENERIC
 235 #define CONFIG_CMD_MMC
 236 #define CONFIG_SYS_MMC_BASE             0xF0000000
 237 #endif
 238
 239 /*
 240  * Physical Memory Map
 241  */
 242 #define CONFIG_NR_DRAM_BANKS    1          /* we have 1 bank of DRAM */
 243 #define PHYS_SDRAM_1            0xa0000000 /* SDRAM Bank #1 */
 244 #define PHYS_SDRAM_1_SIZE       0x04000000 /* 64 MB */
 245 #define PHYS_SDRAM_2            0xa4000000 /* SDRAM Bank #2 */
 246 #define PHYS_SDRAM_2_SIZE       0x00000000 /* 0 MB */
 247 #define PHYS_SDRAM_3            0xa8000000 /* SDRAM Bank #3 */
 248 #define PHYS_SDRAM_3_SIZE       0x00000000 /* 0 MB */
 249 #define PHYS_SDRAM_4            0xac000000 /* SDRAM Bank #4 */
 250 #define PHYS_SDRAM_4_SIZE       0x00000000 /* 0 MB */
 251
 252 #define PHYS_FLASH_1            0x00000000 /* Flash Bank #1 */
 253 #define PHYS_FLASH_2            0x04000000 /* Flash Bank #2 */
 254 #define PHYS_FLASH_SIZE         0x02000000 /* 32 MB */
 255 #define PHYS_FLASH_BANK_SIZE    0x02000000 /* 32 MB Banks */
 256 #define PHYS_FLASH_SECT_SIZE    0x00040000 /* 256 KB sectors (x2) */
 257
 258 #define CONFIG_SYS_DRAM_BASE            0xa0000000
 259 #define CONFIG_SYS_DRAM_SIZE            0x04000000
 260
 261 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 262
 263 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 264 #define CONFIG_SYS_INIT_SP_ADDR         0xfffff800
 265
 266 /*
 267  * GPIO settings
 268  */
 269
 270 #define CONFIG_SYS_GAFR0_L_VAL  0x80001005
 271 #define CONFIG_SYS_GAFR0_U_VAL  0xa5128012
 272 #define CONFIG_SYS_GAFR1_L_VAL  0x699a9558
 273 #define CONFIG_SYS_GAFR1_U_VAL  0xaaa5aa6a
 274 #define CONFIG_SYS_GAFR2_L_VAL  0xaaaaaaaa
 275 #define CONFIG_SYS_GAFR2_U_VAL  0x2
 276 #define CONFIG_SYS_GPCR0_VAL    0x1800400
 277 #define CONFIG_SYS_GPCR1_VAL    0x0
 278 #define CONFIG_SYS_GPCR2_VAL    0x0
 279 #define CONFIG_SYS_GPDR0_VAL    0xc1818440
 280 #define CONFIG_SYS_GPDR1_VAL    0xfcffab82
 281 #define CONFIG_SYS_GPDR2_VAL    0x1ffff
 282 #define CONFIG_SYS_GPSR0_VAL    0x8000
 283 #define CONFIG_SYS_GPSR1_VAL    0x3f0002
 284 #define CONFIG_SYS_GPSR2_VAL    0x1c000
 285
 286 #define CONFIG_SYS_PSSR_VAL             0x20
 287
 288 #define CONFIG_SYS_CCCR                 CCCR_L27|CCCR_M2|CCCR_N10
 289 #define CONFIG_SYS_CKEN                 0x0
 290
 291 /*
 292  * Memory settings
 293  */
 294 #define CONFIG_SYS_MSC0_VAL             0x29DCA4D2
 295 #define CONFIG_SYS_MSC1_VAL             0x43AC494C
 296 #define CONFIG_SYS_MSC2_VAL             0x39D449D4
 297 #define CONFIG_SYS_MDCNFG_VAL           0x090009C9
 298 #define CONFIG_SYS_MDREFR_VAL           0x0085C017
 299 #define CONFIG_SYS_MDMRS_VAL            0x00220022
 300 #define CONFIG_SYS_FLYCNFG_VAL          0x00000000
 301 #define CONFIG_SYS_SXCNFG_VAL           0x00000000
 302
 303 /*
 304  * PCMCIA and CF Interfaces
 305  */
 306 #define CONFIG_SYS_MECR_VAL             0x00000003
 307 #define CONFIG_SYS_MCMEM0_VAL           0x00014405
 308 #define CONFIG_SYS_MCMEM1_VAL           0x00014405
 309 #define CONFIG_SYS_MCATT0_VAL           0x00014405
 310 #define CONFIG_SYS_MCATT1_VAL           0x00014405
 311 #define CONFIG_SYS_MCIO0_VAL            0x00014405
 312 #define CONFIG_SYS_MCIO1_VAL            0x00014405
 313
 314 /*
 315  * FLASH and environment organization
 316  */
 317 #define CONFIG_SYS_FLASH_CFI
 318 #define CONFIG_FLASH_CFI_DRIVER 1
 319
 320 #define CONFIG_SYS_MONITOR_BASE 0
 321 #define CONFIG_SYS_MONITOR_LEN          PHYS_FLASH_SECT_SIZE
 322
 323 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 324 #define CONFIG_SYS_MAX_FLASH_SECT       128  /* max number of sectors on one chip    */
 325
 326 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
 327
 328 /* timeout values are in ticks */
 329 #define CONFIG_SYS_FLASH_ERASE_TOUT     (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
 330 #define CONFIG_SYS_FLASH_WRITE_TOUT     (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 331
 332 /* put cfg at end of flash for now */
 333 #define CONFIG_ENV_IS_IN_FLASH  1
 334  /* Addr of Environment Sector  */
 335 #define CONFIG_ENV_ADDR         (PHYS_FLASH_1 + PHYS_FLASH_SIZE - 0x40000)
 336 #define CONFIG_ENV_SIZE         PHYS_FLASH_SECT_SIZE    /* Total Size of Environment Sector     */
 337 #define CONFIG_ENV_SECT_SIZE    (PHYS_FLASH_SECT_SIZE / 16)
 338
 339 #endif  /* __CONFIG_H */