3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
9 * Copied from lubbock.h
12 * BEC Systems <http://bec-systems.com>
13 * Cliff Brake <cliff.brake@gmail.com>
14 * Configuation settings for the Accelent/Vibren PXA255 IDP
16 * See file CREDITS for list of people who contributed to this
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License as
21 * published by the Free Software Foundation; either version 2 of
22 * the License, or (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
38 #include <asm/arch/pxa-regs.h>
41 * If we are developing, we might want to start U-Boot from RAM
42 * so we MUST NOT initialize critical regs like mem-timing ...
44 #undef CONFIG_SKIP_LOWLEVEL_INIT /* define for developing */
45 #undef CONFIG_SKIP_RELOCATE_UBOOT /* define for developing */
48 * define the following to enable debug blinks. A debug blink function
49 * must be defined in memsetup.S
51 #undef DEBUG_BLINK_ENABLE
52 #undef DEBUG_BLINKC_ENABLE
55 * High Level Configuration Options
58 #define CONFIG_PXA250 1 /* This is an PXA250 CPU */
62 #define CONFIG_SHARP_LM8V31
66 #define CONFIG_DOS_PARTITION 1
67 #define BOARD_LATE_INIT 1
69 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
71 /* we will never enable dcache, because we have to setup MMU first */
72 #define CONFIG_SYS_NO_DCACHE
75 * Size of malloc() pool
77 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
78 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
81 * PXA250 IDP memory map information
84 #define IDP_CS5_ETH_OFFSET 0x03400000
90 #define CONFIG_NET_MULTI
91 #define CONFIG_SMC91111
92 #define CONFIG_SMC91111_BASE (PXA_CS5_PHYS + IDP_CS5_ETH_OFFSET + 0x300)
93 #define CONFIG_SMC_USE_32_BIT 1
94 /* #define CONFIG_SMC_USE_IOFUNCS */
96 /* the following has to be set high -- suspect something is wrong with
97 * with the tftp timeout routines. FIXME!!!
99 #define CONFIG_NET_RETRY_COUNT 100
102 * select serial console configuration
104 #define CONFIG_PXA_SERIAL
105 #define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */
107 /* allow to overwrite serial and ethaddr */
108 #define CONFIG_ENV_OVERWRITE
110 #define CONFIG_BAUDRATE 115200
116 #define CONFIG_BOOTP_BOOTFILESIZE
117 #define CONFIG_BOOTP_BOOTPATH
118 #define CONFIG_BOOTP_GATEWAY
119 #define CONFIG_BOOTP_HOSTNAME
123 * Command line configuration.
125 #include <config_cmd_default.h>
127 #define CONFIG_CMD_FAT
128 #define CONFIG_CMD_DHCP
130 #define CONFIG_BOOTDELAY 3
131 #define CONFIG_BOOTCOMMAND "bootm 40000"
132 #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
134 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
135 #define CONFIG_SETUP_MEMORY_TAGS 1
136 /* #define CONFIG_INITRD_TAG 1 */
139 * Current memory map for Vibren supplied Linux images:
142 * 0 - 0x3ffff (size = 0x40000): bootloader
143 * 0x40000 - 0x13ffff (size = 0x100000): kernel
144 * 0x140000 - 0x1f3ffff (size = 0x1e00000): jffs
147 * 0xa0008000 - kernel is loaded
148 * 0xa3000000 - Uboot runs (48MB into RAM)
152 #define CONFIG_EXTRA_ENV_SETTINGS \
154 "mw.b 0xa0000000 0xff 0x40000; " \
156 "fatload mmc 0 0xa0000000 u-boot.bin; " \
158 "protect off 0x0 0x3ffff; " \
159 "erase 0x0 0x3ffff; " \
160 "cp.b 0xa0000000 0x0 0x40000; " \
163 "prog_uzImage_mmc=" \
164 "mw.b 0xa0000000 0xff 0x100000; " \
166 "fatload mmc 0 0xa0000000 uzImage; " \
168 "protect off 0x40000 0xfffff; " \
169 "erase 0x40000 0xfffff; " \
170 "cp.b 0xa0000000 0x40000 0x100000; " \
173 "mw.b 0xa0000000 0xff 0x1e00000; " \
175 "fatload mmc 0 0xa0000000 root.jffs; " \
177 "protect off 0x140000 0x1f3ffff; " \
178 "erase 0x140000 0x1f3ffff; " \
179 "cp.b 0xa0000000 0x140000 0x1e00000; " \
183 "fatload mmc 0 0xa1000000 uzImage && " \
185 "bootm 0xa1000000; " \
188 "mw.b 0xa0000000 0xff 0x100000; " \
189 "if bootp 0xa0000000 u-boot.bin; " \
191 "protect off 0x0 0x3ffff; " \
192 "erase 0x0 0x3ffff; " \
193 "cp.b 0xa0000000 0x0 0x40000; " \
196 "prog_uzImage_net=" \
197 "mw.b 0xa0000000 0xff 0x100000; " \
198 "if bootp 0xa0000000 uzImage; " \
200 "protect off 0x40000 0xfffff; " \
201 "erase 0x40000 0xfffff; " \
202 "cp.b 0xa0000000 0x40000 0x100000; " \
205 "mw.b 0xa0000000 0xff 0x1e00000; " \
206 "if bootp 0xa0000000 root.jffs; " \
208 "protect off 0x140000 0x1f3ffff; " \
209 "erase 0x140000 0x1f3ffff; " \
210 "cp.b 0xa0000000 0x140000 0x1e00000; " \
218 #if defined(CONFIG_CMD_KGDB)
219 #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
220 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
224 * Miscellaneous configurable options
226 #define CONFIG_SYS_HUSH_PARSER 1
227 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
229 #define CONFIG_SYS_LONGHELP /* undef to save memory */
230 #ifdef CONFIG_SYS_HUSH_PARSER
231 #define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */
233 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
235 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
236 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
237 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
238 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
239 #define CONFIG_SYS_DEVICE_NULLDEV 1
241 #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
242 #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
244 #define CONFIG_SYS_LOAD_ADDR 0xa0800000 /* default load address */
246 #define CONFIG_SYS_HZ 1000
247 #define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
249 #define RTC 1 /* enable 32KHz osc */
251 /* valid baudrates */
252 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
255 #define CONFIG_PXA_MMC
256 #define CONFIG_CMD_MMC
257 #define CONFIG_SYS_MMC_BASE 0xF0000000
263 * The stack sizes are set up in start.S using the settings below
265 #define CONFIG_STACKSIZE (128*1024) /* regular stack */
266 #ifdef CONFIG_USE_IRQ
267 #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
268 #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
272 * Physical Memory Map
274 #define CONFIG_NR_DRAM_BANKS 4 /* we have 1 banks of DRAM */
275 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
276 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
277 #define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
278 #define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
279 #define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
280 #define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
281 #define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
282 #define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
284 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
285 #define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
286 #define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
287 #define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */
288 #define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
290 #define CONFIG_SYS_DRAM_BASE 0xa0000000
291 #define CONFIG_SYS_DRAM_SIZE 0x04000000
293 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
299 #define CONFIG_SYS_GAFR0_L_VAL 0x80001005
300 #define CONFIG_SYS_GAFR0_U_VAL 0xa5128012
301 #define CONFIG_SYS_GAFR1_L_VAL 0x699a9558
302 #define CONFIG_SYS_GAFR1_U_VAL 0xaaa5aa6a
303 #define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
304 #define CONFIG_SYS_GAFR2_U_VAL 0x2
305 #define CONFIG_SYS_GPCR0_VAL 0x1800400
306 #define CONFIG_SYS_GPCR1_VAL 0x0
307 #define CONFIG_SYS_GPCR2_VAL 0x0
308 #define CONFIG_SYS_GPDR0_VAL 0xc1818440
309 #define CONFIG_SYS_GPDR1_VAL 0xfcffab82
310 #define CONFIG_SYS_GPDR2_VAL 0x1ffff
311 #define CONFIG_SYS_GPSR0_VAL 0x8000
312 #define CONFIG_SYS_GPSR1_VAL 0x3f0002
313 #define CONFIG_SYS_GPSR2_VAL 0x1c000
315 #define CONFIG_SYS_PSSR_VAL 0x20
320 #define CONFIG_SYS_MSC0_VAL 0x29DCA4D2
321 #define CONFIG_SYS_MSC1_VAL 0x43AC494C
322 #define CONFIG_SYS_MSC2_VAL 0x39D449D4
323 #define CONFIG_SYS_MDCNFG_VAL 0x090009C9
324 #define CONFIG_SYS_MDREFR_VAL 0x0085C017
325 #define CONFIG_SYS_MDMRS_VAL 0x00220022
328 * PCMCIA and CF Interfaces
330 #define CONFIG_SYS_MECR_VAL 0x00000003
331 #define CONFIG_SYS_MCMEM0_VAL 0x00014405
332 #define CONFIG_SYS_MCMEM1_VAL 0x00014405
333 #define CONFIG_SYS_MCATT0_VAL 0x00014405
334 #define CONFIG_SYS_MCATT1_VAL 0x00014405
335 #define CONFIG_SYS_MCIO0_VAL 0x00014405
336 #define CONFIG_SYS_MCIO1_VAL 0x00014405
339 * FLASH and environment organization
341 #define CONFIG_SYS_FLASH_CFI
342 #define CONFIG_FLASH_CFI_DRIVER 1
344 #define CONFIG_SYS_MONITOR_BASE 0
345 #define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE
347 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
348 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
350 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
352 /* timeout values are in ticks */
353 #define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
354 #define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */
356 /* put cfg at end of flash for now */
357 #define CONFIG_ENV_IS_IN_FLASH 1
358 /* Addr of Environment Sector */
359 #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SIZE - 0x40000)
360 #define CONFIG_ENV_SIZE PHYS_FLASH_SECT_SIZE /* Total Size of Environment Sector */
361 #define CONFIG_ENV_SECT_SIZE (PHYS_FLASH_SECT_SIZE / 16)
363 #endif /* __CONFIG_H */