include/configs/px30_common.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2017 Rockchip Electronics Co., Ltd
   4  */
   5
   6 #ifndef __CONFIG_PX30_COMMON_H
   7 #define __CONFIG_PX30_COMMON_H
   8
   9 #include "rockchip-common.h"
  10
  11 #define CONFIG_SYS_CBSIZE               1024
  12 #define CONFIG_SKIP_LOWLEVEL_INIT
  13
  14 #define CONFIG_SYS_NS16550_MEM32
  15
  16 #define CONFIG_ROCKCHIP_STIMER_BASE     0xff220020
  17 #define COUNTER_FREQUENCY               24000000
  18
  19 /* FIXME: ff020000 is pmu_mem (10k), while ff0e0000 is regular int_mem */
  20 #define CONFIG_IRAM_BASE                0xff020000
  21
  22 #define CONFIG_SYS_INIT_SP_ADDR         0x00400000
  23 #define CONFIG_SYS_LOAD_ADDR            0x00800800
  24 #define CONFIG_SPL_STACK                0x00400000
  25 #define CONFIG_SPL_MAX_SIZE             0x20000
  26 #define CONFIG_SPL_BSS_START_ADDR       0x4000000
  27 #define CONFIG_SPL_BSS_MAX_SIZE         0x4000
  28 #define CONFIG_SYS_BOOTM_LEN            (64 << 20)      /* 64M */
  29
  30 #define GICD_BASE                       0xff131000
  31 #define GICC_BASE                       0xff132000
  32
  33 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* 64M */
  34
  35 /* MMC/SD IP block */
  36 //#define CONFIG_BOUNCE_BUFFER
  37
  38 #define CONFIG_SYS_SDRAM_BASE           0
  39 #define SDRAM_MAX_SIZE                  0xff000000
  40 #define SDRAM_BANK_SIZE                 (2UL << 30)
  41
  42 #ifndef CONFIG_SPL_BUILD
  43
  44 #define ENV_MEM_LAYOUT_SETTINGS \
  45         "scriptaddr=0x00500000\0" \
  46         "pxefile_addr_r=0x00600000\0" \
  47         "fdt_addr_r=0x08300000\0" \
  48         "kernel_addr_r=0x00280000\0" \
  49         "kernel_addr_c=0x03e80000\0" \
  50         "ramdisk_addr_r=0x0a200000\0"
  51
  52 #include <config_distro_bootcmd.h>
  53 #define CONFIG_EXTRA_ENV_SETTINGS \
  54         ENV_MEM_LAYOUT_SETTINGS \
  55         "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
  56         "partitions=" PARTS_DEFAULT \
  57         ROCKCHIP_DEVICE_SETTINGS \
  58         BOOTENV
  59
  60 #endif
  61
  62 #endif