1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
6 #ifndef __CONFIG_PX30_COMMON_H
7 #define __CONFIG_PX30_COMMON_H
9 #include "rockchip-common.h"
11 #define CONFIG_SYS_CBSIZE 1024
12 #define CONFIG_SKIP_LOWLEVEL_INIT
14 #define CONFIG_SYS_NS16550_MEM32
16 #define CONFIG_ROCKCHIP_STIMER_BASE 0xff220020
17 #define COUNTER_FREQUENCY 24000000
19 /* FIXME: ff020000 is pmu_mem (10k), while ff0e0000 is regular int_mem */
20 #define CONFIG_IRAM_BASE 0xff020000
22 #define CONFIG_SYS_INIT_SP_ADDR 0x00400000
23 #define CONFIG_SYS_LOAD_ADDR 0x00800800
24 #define CONFIG_SPL_STACK 0x00400000
25 #define CONFIG_SPL_MAX_SIZE 0x20000
26 #define CONFIG_SPL_BSS_START_ADDR 0x4000000
27 #define CONFIG_SPL_BSS_MAX_SIZE 0x4000
28 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
30 #define GICD_BASE 0xff131000
31 #define GICC_BASE 0xff132000
33 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
35 #define CONFIG_SYS_SDRAM_BASE 0
36 #define SDRAM_MAX_SIZE 0xff000000
37 #define SDRAM_BANK_SIZE (2UL << 30)
39 #ifndef CONFIG_SPL_BUILD
41 #define ENV_MEM_LAYOUT_SETTINGS \
42 "scriptaddr=0x00500000\0" \
43 "pxefile_addr_r=0x00600000\0" \
44 "fdt_addr_r=0x08300000\0" \
45 "kernel_addr_r=0x00280000\0" \
46 "kernel_addr_c=0x03e80000\0" \
47 "ramdisk_addr_r=0x0a200000\0"
49 #include <config_distro_bootcmd.h>
50 #define CONFIG_EXTRA_ENV_SETTINGS \
51 ENV_MEM_LAYOUT_SETTINGS \
52 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
53 "partitions=" PARTS_DEFAULT \
54 ROCKCHIP_DEVICE_SETTINGS \