include/configs/px30_common.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2017 Rockchip Electronics Co., Ltd
   4  */
   5
   6 #ifndef __CONFIG_PX30_COMMON_H
   7 #define __CONFIG_PX30_COMMON_H
   8
   9 #include "rockchip-common.h"
  10
  11 #define CONFIG_SYS_CBSIZE               1024
  12
  13 #define CONFIG_SYS_NS16550_MEM32
  14
  15 #define CONFIG_ROCKCHIP_STIMER_BASE     0xff220020
  16 #define COUNTER_FREQUENCY               24000000
  17
  18 /* FIXME: ff020000 is pmu_mem (10k), while ff0e0000 is regular int_mem */
  19 #define CONFIG_IRAM_BASE                0xff020000
  20
  21 #define CONFIG_SYS_INIT_SP_ADDR         0x00400000
  22 #define CONFIG_SPL_STACK                0x00400000
  23 #define CONFIG_SPL_MAX_SIZE             0x20000
  24 #define CONFIG_SPL_BSS_START_ADDR       0x4000000
  25 #define CONFIG_SPL_BSS_MAX_SIZE         0x4000
  26 #define CONFIG_SYS_BOOTM_LEN            (64 << 20)      /* 64M */
  27
  28 #define GICD_BASE                       0xff131000
  29 #define GICC_BASE                       0xff132000
  30
  31 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* 64M */
  32
  33 #define CONFIG_SYS_SDRAM_BASE           0
  34 #define SDRAM_MAX_SIZE                  0xff000000
  35 #define SDRAM_BANK_SIZE                 (2UL << 30)
  36
  37 #ifndef CONFIG_SPL_BUILD
  38
  39 #define ENV_MEM_LAYOUT_SETTINGS \
  40         "scriptaddr=0x00500000\0" \
  41         "pxefile_addr_r=0x00600000\0" \
  42         "fdt_addr_r=0x08300000\0" \
  43         "kernel_addr_r=0x00280000\0" \
  44         "kernel_addr_c=0x03e80000\0" \
  45         "ramdisk_addr_r=0x0a200000\0"
  46
  47 #include <config_distro_bootcmd.h>
  48 #define CONFIG_EXTRA_ENV_SETTINGS \
  49         ENV_MEM_LAYOUT_SETTINGS \
  50         "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
  51         "partitions=" PARTS_DEFAULT \
  52         ROCKCHIP_DEVICE_SETTINGS \
  53         BOOTENV
  54
  55 #endif
  56
  57 #endif