include/configs/presidio_asic.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2020 Cortina Access Inc.
   4  *
   5  * Configuration for Cortina-Access Presidio board
   6  */
   7
   8 #ifndef __PRESIDIO_ASIC_H
   9 #define __PRESIDIO_ASIC_H
  10
  11 #define CONFIG_SYS_INIT_SP_ADDR         0x00100000
  12 #define CONFIG_SYS_BOOTM_LEN            0x00c00000
  13
  14 /* Generic Timer Definitions */
  15 #define CONFIG_SYS_TIMER_RATE           25000000
  16 #define CONFIG_SYS_TIMER_COUNTER        0xf4321008
  17
  18 /* note: arch/arm/cpu/armv8/start.S which references GICD_BASE/GICC_BASE
  19  * does not yet support DT. Thus define it here.
  20  */
  21 #define GICD_BASE                       0xf7011000
  22 #define GICC_BASE                       0xf7012000
  23
  24 #define CONFIG_SYS_TIMER_BASE           0xf4321000
  25
  26 /* Use external clock source */
  27 #define PRESIDIO_APB_CLK                125000000
  28 #define CORTINA_PER_IO_FREQ             PRESIDIO_APB_CLK
  29
  30 /* Cortina Serial Configuration */
  31 #define CORTINA_UART_CLOCK              (PRESIDIO_APB_CLK)
  32 #define CORTINA_SERIAL_PORTS            {(void *)CONFIG_SYS_SERIAL0, \
  33                                          (void *)CONFIG_SYS_SERIAL1}
  34
  35 #define CONFIG_SYS_SERIAL0              PER_UART0_CFG
  36 #define CONFIG_SYS_SERIAL1              PER_UART1_CFG
  37
  38 /* SDRAM Bank #1 */
  39 #define DDR_BASE                        0x00000000
  40 #define PHYS_SDRAM_1                    DDR_BASE
  41 #define PHYS_SDRAM_1_SIZE               0x80000000 /* 2GB */
  42 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
  43
  44 /* Console I/O Buffer Size */
  45
  46 #define KSEG1_ATU_XLAT(x) (x)
  47
  48 /* HW REG ADDR */
  49 #define NI_READ_POLL_COUNT                      1000
  50 #define CA_NI_MDIO_REG_BASE                     0xF4338
  51 #define NI_HV_GLB_MAC_ADDR_CFG0_OFFSET          0x010
  52 #define NI_HV_GLB_MAC_ADDR_CFG1_OFFSET          0x014
  53 #define NI_HV_PT_BASE                           0x400
  54 #define NI_HV_XRAM_BASE                         0x820
  55 #define GLOBAL_BLOCK_RESET_OFFSET               0x04
  56 #define GLOBAL_GLOBAL_CONFIG_OFFSET             0x20
  57 #define GLOBAL_IO_DRIVE_CONTROL_OFFSET          0x4c
  58
  59 /* max command args */
  60 #define CONFIG_EXTRA_ENV_SETTINGS       "silent=y\0"
  61
  62 /* nand driver parameters */
  63 #ifdef CONFIG_TARGET_PRESIDIO_ASIC
  64         #define CONFIG_SYS_MAX_NAND_DEVICE      1
  65         #define CONFIG_SYS_NAND_BASE            CONFIG_SYS_FLASH_BASE
  66         #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
  67 #endif
  68
  69 #endif /* __PRESIDIO_ASIC_H */