1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2020 Cortina Access Inc.
5 * Configuration for Cortina-Access Presidio board
8 #ifndef __PRESIDIO_ASIC_H
9 #define __PRESIDIO_ASIC_H
11 #define CONFIG_REMAKE_ELF
13 #define CONFIG_SYS_INIT_SP_ADDR 0x00100000
14 #define CONFIG_SYS_BOOTM_LEN 0x00c00000
16 /* Generic Timer Definitions */
17 #define COUNTER_FREQUENCY 25000000
18 #define CONFIG_SYS_TIMER_RATE COUNTER_FREQUENCY
19 #define CONFIG_SYS_TIMER_COUNTER 0xf4321008
21 /* note: arch/arm/cpu/armv8/start.S which references GICD_BASE/GICC_BASE
22 * does not yet support DT. Thus define it here.
24 #define GICD_BASE 0xf7011000
25 #define GICC_BASE 0xf7012000
27 #define CONFIG_SYS_TIMER_BASE 0xf4321000
29 /* Use external clock source */
30 #define PRESIDIO_APB_CLK 125000000
31 #define CORTINA_PER_IO_FREQ PRESIDIO_APB_CLK
33 /* Cortina Serial Configuration */
34 #define CORTINA_UART_CLOCK (PRESIDIO_APB_CLK)
35 #define CORTINA_SERIAL_PORTS {(void *)CONFIG_SYS_SERIAL0, \
36 (void *)CONFIG_SYS_SERIAL1}
38 #define CONFIG_SYS_SERIAL0 PER_UART0_CFG
39 #define CONFIG_SYS_SERIAL1 PER_UART1_CFG
42 #define CONFIG_BOOTP_BOOTFILESIZE
45 #define DDR_BASE 0x00000000
46 #define PHYS_SDRAM_1 DDR_BASE
47 #define PHYS_SDRAM_1_SIZE 0x80000000 /* 2GB */
48 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
50 /* Console I/O Buffer Size */
51 #define CONFIG_SYS_CBSIZE 256
52 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
53 sizeof(CONFIG_SYS_PROMPT) + 16)
54 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
56 #define KSEG1_ATU_XLAT(x) (x)
59 #define NI_READ_POLL_COUNT 1000
60 #define CA_NI_MDIO_REG_BASE 0xF4338
61 #define NI_HV_GLB_MAC_ADDR_CFG0_OFFSET 0x010
62 #define NI_HV_GLB_MAC_ADDR_CFG1_OFFSET 0x014
63 #define NI_HV_PT_BASE 0x400
64 #define NI_HV_XRAM_BASE 0x820
65 #define GLOBAL_BLOCK_RESET_OFFSET 0x04
66 #define GLOBAL_GLOBAL_CONFIG_OFFSET 0x20
67 #define GLOBAL_IO_DRIVE_CONTROL_OFFSET 0x4c
69 /* max command args */
70 #define CONFIG_SYS_MAXARGS 64
71 #define CONFIG_EXTRA_ENV_SETTINGS "silent=y\0"
73 /* nand driver parameters */
74 #ifdef CONFIG_TARGET_PRESIDIO_ASIC
75 #define CONFIG_SYS_MAX_NAND_DEVICE 1
76 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_FLASH_BASE
77 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
80 #endif /* __PRESIDIO_ASIC_H */