include/configs/presidio_asic.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2020 Cortina Access Inc.
   4  *
   5  * Configuration for Cortina-Access Presidio board
   6  */
   7
   8 #ifndef __PRESIDIO_ASIC_H
   9 #define __PRESIDIO_ASIC_H
  10
  11 #define CONFIG_REMAKE_ELF
  12
  13 #define CONFIG_SUPPORT_RAW_INITRD
  14
  15 #define CONFIG_SYS_INIT_SP_ADDR         0x00100000
  16 #define CONFIG_SYS_BOOTM_LEN            0x00c00000
  17
  18 /* Generic Timer Definitions */
  19 #define COUNTER_FREQUENCY               25000000
  20 #define CONFIG_SYS_TIMER_RATE           COUNTER_FREQUENCY
  21 #define CONFIG_SYS_TIMER_COUNTER        0xf4321008
  22
  23 /* note: arch/arm/cpu/armv8/start.S which references GICD_BASE/GICC_BASE
  24  * does not yet support DT. Thus define it here.
  25  */
  26 #define GICD_BASE                       0xf7011000
  27 #define GICC_BASE                       0xf7012000
  28
  29 /* Size of malloc() pool */
  30 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + (8 << 20))
  31
  32 #define CONFIG_SYS_TIMER_BASE           0xf4321000
  33
  34 /* Use external clock source */
  35 #define PRESIDIO_APB_CLK                125000000
  36 #define CORTINA_PER_IO_FREQ             PRESIDIO_APB_CLK
  37
  38 /* Cortina Serial Configuration */
  39 #define CORTINA_UART_CLOCK              (PRESIDIO_APB_CLK)
  40 #define CORTINA_SERIAL_PORTS            {(void *)CONFIG_SYS_SERIAL0, \
  41                                          (void *)CONFIG_SYS_SERIAL1}
  42
  43 #define CONFIG_SYS_SERIAL0              PER_UART0_CFG
  44 #define CONFIG_SYS_SERIAL1              PER_UART1_CFG
  45
  46 /* BOOTP options */
  47 #define CONFIG_BOOTP_BOOTFILESIZE
  48
  49 /* Miscellaneous configurable options */
  50 #define CONFIG_LAST_STAGE_INIT
  51
  52 /* SDRAM Bank #1 */
  53 #define DDR_BASE                        0x00000000
  54 #define PHYS_SDRAM_1                    DDR_BASE
  55 #define PHYS_SDRAM_1_SIZE               0x80000000 /* 2GB */
  56 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
  57
  58 /* Console I/O Buffer Size */
  59 #define CONFIG_SYS_CBSIZE               256
  60 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
  61                                         sizeof(CONFIG_SYS_PROMPT) + 16)
  62 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
  63
  64 #define KSEG1_ATU_XLAT(x) (x)
  65
  66 /* HW REG ADDR */
  67 #define NI_READ_POLL_COUNT                      1000
  68 #define CA_NI_MDIO_REG_BASE                     0xF4338
  69 #define NI_HV_GLB_MAC_ADDR_CFG0_OFFSET          0x010
  70 #define NI_HV_GLB_MAC_ADDR_CFG1_OFFSET          0x014
  71 #define NI_HV_PT_BASE                           0x400
  72 #define NI_HV_XRAM_BASE                         0x820
  73 #define GLOBAL_BLOCK_RESET_OFFSET               0x04
  74 #define GLOBAL_GLOBAL_CONFIG_OFFSET             0x20
  75 #define GLOBAL_IO_DRIVE_CONTROL_OFFSET          0x4c
  76
  77 /* max command args */
  78 #define CONFIG_SYS_MAXARGS              64
  79 #define CONFIG_EXTRA_ENV_SETTINGS       "silent=y\0"
  80
  81 /* nand driver parameters */
  82 #ifdef CONFIG_TARGET_PRESIDIO_ASIC
  83         #define CONFIG_SYS_NAND_ONFI_DETECTION
  84         #define CONFIG_SYS_MAX_NAND_DEVICE      1
  85         #define CONFIG_SYS_NAND_MAX_CHIPS       1
  86         #define CONFIG_SYS_NAND_BASE            CONFIG_SYS_FLASH_BASE
  87         #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
  88 #endif
  89
  90 #endif /* __PRESIDIO_ASIC_H */