1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2020 Cortina Access Inc.
5 * Configuration for Cortina-Access Presidio board
8 #ifndef __PRESIDIO_ASIC_H
9 #define __PRESIDIO_ASIC_H
11 #define CONFIG_SYS_INIT_SP_ADDR 0x00100000
12 #define CONFIG_SYS_BOOTM_LEN 0x00c00000
14 /* Generic Timer Definitions */
15 #define COUNTER_FREQUENCY 25000000
16 #define CONFIG_SYS_TIMER_RATE COUNTER_FREQUENCY
17 #define CONFIG_SYS_TIMER_COUNTER 0xf4321008
19 /* note: arch/arm/cpu/armv8/start.S which references GICD_BASE/GICC_BASE
20 * does not yet support DT. Thus define it here.
22 #define GICD_BASE 0xf7011000
23 #define GICC_BASE 0xf7012000
25 #define CONFIG_SYS_TIMER_BASE 0xf4321000
27 /* Use external clock source */
28 #define PRESIDIO_APB_CLK 125000000
29 #define CORTINA_PER_IO_FREQ PRESIDIO_APB_CLK
31 /* Cortina Serial Configuration */
32 #define CORTINA_UART_CLOCK (PRESIDIO_APB_CLK)
33 #define CORTINA_SERIAL_PORTS {(void *)CONFIG_SYS_SERIAL0, \
34 (void *)CONFIG_SYS_SERIAL1}
36 #define CONFIG_SYS_SERIAL0 PER_UART0_CFG
37 #define CONFIG_SYS_SERIAL1 PER_UART1_CFG
40 #define DDR_BASE 0x00000000
41 #define PHYS_SDRAM_1 DDR_BASE
42 #define PHYS_SDRAM_1_SIZE 0x80000000 /* 2GB */
43 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
45 /* Console I/O Buffer Size */
46 #define CONFIG_SYS_CBSIZE 256
47 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
48 sizeof(CONFIG_SYS_PROMPT) + 16)
49 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
51 #define KSEG1_ATU_XLAT(x) (x)
54 #define NI_READ_POLL_COUNT 1000
55 #define CA_NI_MDIO_REG_BASE 0xF4338
56 #define NI_HV_GLB_MAC_ADDR_CFG0_OFFSET 0x010
57 #define NI_HV_GLB_MAC_ADDR_CFG1_OFFSET 0x014
58 #define NI_HV_PT_BASE 0x400
59 #define NI_HV_XRAM_BASE 0x820
60 #define GLOBAL_BLOCK_RESET_OFFSET 0x04
61 #define GLOBAL_GLOBAL_CONFIG_OFFSET 0x20
62 #define GLOBAL_IO_DRIVE_CONTROL_OFFSET 0x4c
64 /* max command args */
65 #define CONFIG_SYS_MAXARGS 64
66 #define CONFIG_EXTRA_ENV_SETTINGS "silent=y\0"
68 /* nand driver parameters */
69 #ifdef CONFIG_TARGET_PRESIDIO_ASIC
70 #define CONFIG_SYS_MAX_NAND_DEVICE 1
71 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_FLASH_BASE
72 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
75 #endif /* __PRESIDIO_ASIC_H */