3 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
10 * Advent Networks, Inc. <http://www.adventnetworks.com>
11 * Jay Monkman <jtm@smoothsmoothie.com>
13 * Configuation settings for the WindRiver PPMC8260 board.
15 * See file CREDITS for list of people who contributed to this
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
37 /*****************************************************************************
39 * These settings must match the way _your_ board is set up
41 *****************************************************************************/
43 /* What is the oscillator's (UX2) frequency in Hz? */
44 #define CONFIG_8260_CLKIN (66 * 1000 * 1000)
46 /*-----------------------------------------------------------------------
47 * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
48 *-----------------------------------------------------------------------
49 * What should MODCK_H be? It is dependent on the oscillator
50 * frequency, MODCK[1-3], and desired CPM and core frequencies.
51 * Here are some example values (all frequencies are in MHz):
53 * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8
54 * ------- ---------- --- --- ---- ----- ----- -----
55 * 0x2 0x2 33 133 133 Close Open Close
56 * 0x2 0x3 33 133 166 Close Open Open
57 * 0x2 0x4 33 133 200 Open Close Close
58 * 0x2 0x5 33 133 233 Open Close Open
59 * 0x2 0x6 33 133 266 Open Open Close
61 * 0x5 0x5 66 133 133 Open Close Open
62 * 0x5 0x6 66 133 166 Open Open Close
63 * 0x5 0x7 66 133 200 Open Open Open
64 * 0x6 0x0 66 133 233 Close Close Close
65 * 0x6 0x1 66 133 266 Close Close Open
66 * 0x6 0x2 66 133 300 Close Open Close
68 #define CFG_PPMC_MODCK_H 0x05
70 /* Define this if you want to boot from 0x00000100. If you don't define
71 * this, you will need to program the bootloader to 0xfff00000, and
72 * get the hardware reset config words at 0xfe000000. The simplest
73 * way to do that is to program the bootloader at both addresses.
74 * It is suggested that you just let U-Boot live at 0x00000000.
76 #define CFG_PPMC_BOOT_LOW 1
78 /* What should the base address of the main FLASH be and how big is
79 * it (in MBytes)? This must contain TEXT_BASE from board/ppmc8260/config.mk
80 * The main FLASH is whichever is connected to *CS0. U-Boot expects
81 * this to be the SIMM.
83 #define CFG_FLASH0_BASE 0xFE000000
84 #define CFG_FLASH0_SIZE 16
86 /* What should be the base address of the first SDRAM DIMM and how big is
89 #define CFG_SDRAM0_BASE 0x00000000
90 #define CFG_SDRAM0_SIZE 128
92 /* What should be the base address of the second SDRAM DIMM and how big is
95 #define CFG_SDRAM1_BASE 0x08000000
96 #define CFG_SDRAM1_SIZE 128
98 /* What should be the base address of the on board SDRAM and how big is
101 #define CFG_SDRAM2_BASE 0x38000000
102 #define CFG_SDRAM2_SIZE 16
104 /* What should be the base address of the MAILBOX and how big is it
106 * The eeprom lives at CFG_MAILBOX_BASE + 0x80000000
108 #define CFG_MAILBOX_BASE 0x32000000
109 #define CFG_MAILBOX_SIZE 8192
111 /* What is the base address of the I/O select lines and how big is it
115 #define CFG_IOSELECT_BASE 0xE0000000
116 #define CFG_IOSELECT_SIZE 32
119 /* What should be the base address of the LEDs and switch S0?
120 * If you don't want them enabled, don't define this.
122 #define CFG_LED_BASE 0xF1000000
125 * PPMC8260 with 256 16 MB DIMM:
127 * 0x0000 0000 Exception Vector code, 8k
130 * 0x0000 2000 Free for Application Use
136 * 0x0FF5 FF30 Monitor Stack (Growing downward)
137 * Monitor Stack Buffer (0x80)
138 * 0x0FF5 FFB0 Board Info Data
139 * 0x0FF6 0000 Malloc Arena
140 * : CFG_ENV_SECT_SIZE, 256k
141 * : CFG_MALLOC_LEN, 128k
142 * 0x0FFC 0000 RAM Copy of Monitor Code
143 * : CFG_MONITOR_LEN, 256k
144 * 0x0FFF FFFF [End of RAM], CFG_SDRAM_SIZE - 1
149 * select serial console configuration
151 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
152 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
155 * if CONFIG_CONS_NONE is defined, then the serial console routines must
157 * The console can be on SMC1 or SMC2
159 #define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */
160 #undef CONFIG_CONS_ON_SCC /* define if console on SCC */
161 #undef CONFIG_CONS_NONE /* define if console on neither */
162 #define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
165 * select ethernet configuration
167 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
168 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
171 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
172 * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
173 * from CONFIG_COMMANDS to remove support for networking.
176 #undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */
177 #define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */
178 #undef CONFIG_ETHER_NONE /* define if ethernet on neither */
179 #define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
180 #define CONFIG_MII /* MII PHY management */
181 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
183 * Port pins used for bit-banged MII communictions (if applicable).
185 #define MDIO_PORT 2 /* Port C */
186 #define MDIO_ACTIVE (iop->pdir |= 0x00400000)
187 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
188 #define MDIO_READ ((iop->pdat & 0x00400000) != 0)
190 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
191 else iop->pdat &= ~0x00400000
193 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
194 else iop->pdat &= ~0x00200000
196 #define MIIDELAY udelay(1)
199 /* Define this to reserve an entire FLASH sector (256 KB) for
200 * environment variables. Otherwise, the environment will be
201 * put in the same sector as U-Boot, and changing variables
202 * will erase U-Boot temporarily
204 #define CFG_ENV_IN_OWN_SECT 1
206 /* Define to allow the user to overwrite serial and ethaddr */
207 #define CONFIG_ENV_OVERWRITE
209 /* What should the console's baud rate be? */
210 #define CONFIG_BAUDRATE 9600
212 /* Ethernet MAC address */
214 #define CONFIG_ETHADDR 00:a0:1e:90:2b:00
216 /* Define this to set the last octet of the ethernet address
217 * from the DS0-DS7 switch and light the leds with the result
218 * The DS0-DS7 switch and the leds are backwards with respect
219 * to each other. DS7 is on the board edge side of both the
220 * led strip and the DS0-DS7 switch.
222 #define CONFIG_MISC_INIT_R
224 /* Set to a positive value to delay for running BOOTCOMMAND */
225 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
228 /* Be selective on what keys can delay or stop the autoboot process
231 # define CONFIG_AUTOBOOT_KEYED
232 # define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, press \" \" to stop\n"
233 # define CONFIG_AUTOBOOT_STOP_STR " "
234 # undef CONFIG_AUTOBOOT_DELAY_STR
235 # define DEBUG_BOOTKEYS 0
238 /* Define a command string that is automatically executed when no character
239 * is read on the console interface withing "Boot Delay" after reset.
241 #undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */
242 #define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */
244 #ifdef CONFIG_BOOT_ROOT_INITRD
245 #define CONFIG_BOOTCOMMAND \
249 "setenv bootargs root=/dev/ram0 rw " \
250 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
252 #endif /* CONFIG_BOOT_ROOT_INITRD */
254 #ifdef CONFIG_BOOT_ROOT_NFS
255 #define CONFIG_BOOTCOMMAND \
259 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
260 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
262 #endif /* CONFIG_BOOT_ROOT_NFS */
264 /* Add support for a few extra bootp options like:
268 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
269 CONFIG_BOOTP_BOOTFILESIZE | \
272 /* undef this to save memory */
275 /* Monitor Command Prompt */
276 #define CFG_PROMPT "=> "
278 /* What U-Boot subsytems do you want enabled? */
279 #define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
289 /* Where do the internal registers live? */
290 #define CFG_IMMR 0xf0000000
292 /*****************************************************************************
294 * You should not have to modify any of the following settings
296 *****************************************************************************/
298 #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
299 #define CONFIG_PPMC8260 1 /* on an Wind River PPMC8260 Board */
300 #define CONFIG_CPM2 1 /* Has a CPM2 */
302 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
303 #include <cmd_confdefs.h>
306 * Miscellaneous configurable options
308 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
309 # define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
311 # define CFG_CBSIZE 256 /* Console I/O Buffer Size */
314 /* Print Buffer Size */
315 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
317 #define CFG_MAXARGS 32 /* max number of command args */
319 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
321 #define CFG_LOAD_ADDR 0x140000 /* default load address */
322 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
324 #define CFG_MEMTEST_START 0x2000 /* memtest works from the end of */
325 /* the exception vector table */
326 /* to the end of the DRAM */
327 /* less monitor and malloc area */
328 #define CFG_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */
329 #define CFG_MEM_END_USAGE ( CFG_MONITOR_LEN \
331 + CFG_ENV_SECT_SIZE \
334 #define CFG_MEMTEST_END ( CFG_SDRAM_SIZE * 1024 * 1024 \
335 - CFG_MEM_END_USAGE )
337 /* valid baudrates */
338 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
341 * Low Level Configuration Settings
342 * (address mappings, register initial values, etc.)
343 * You should know what you are doing if you make changes here.
346 #if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
348 * Attention: This is board specific
352 #define CFG_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 |\
355 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
357 * Attention: this is board-specific
360 * - Select bus for bd/buffers (see 28-13)
361 * - Enable Full Duplex in FSMR
363 #define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
364 #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
365 #define CFG_CPMFCR_RAMTYPE 0
366 #define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
367 #endif /* CONFIG_ETHER_INDEX */
369 #define CFG_FLASH_BASE CFG_FLASH0_BASE
370 #define CFG_FLASH_SIZE CFG_FLASH0_SIZE
371 #define CFG_SDRAM_BASE CFG_SDRAM0_BASE
372 #define CFG_SDRAM_SIZE (CFG_SDRAM0_SIZE + CFG_SDRAM1_SIZE)
374 /*-----------------------------------------------------------------------
375 * Hard Reset Configuration Words
377 #if defined(CFG_PPMC_BOOT_LOW)
378 # define CFG_PPMC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
380 # define CFG_PPMC_HRCW_BOOT_FLAGS (0)
381 #endif /* defined(CFG_PPMC_BOOT_LOW) */
383 /* get the HRCW ISB field from CFG_IMMR */
384 #define CFG_PPMC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) | \
385 ((CFG_IMMR & 0x01000000) >> 7) | \
386 ((CFG_IMMR & 0x00100000) >> 4) )
388 #define CFG_HRCW_MASTER ( HRCW_EBM | \
392 CFG_PPMC_HRCW_IMMR | \
397 (CFG_PPMC_MODCK_H & HRCW_MODCK_H1111) | \
398 CFG_PPMC_HRCW_BOOT_FLAGS )
401 #define CFG_HRCW_SLAVE1 0
402 #define CFG_HRCW_SLAVE2 0
403 #define CFG_HRCW_SLAVE3 0
404 #define CFG_HRCW_SLAVE4 0
405 #define CFG_HRCW_SLAVE5 0
406 #define CFG_HRCW_SLAVE6 0
407 #define CFG_HRCW_SLAVE7 0
409 /*-----------------------------------------------------------------------
410 * Definitions for initial stack pointer and data area (in DPRAM)
412 #define CFG_INIT_RAM_ADDR CFG_IMMR
413 #define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
414 #define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */
415 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
416 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
418 /*-----------------------------------------------------------------------
419 * Start addresses for the final memory configuration
420 * (Set up by the startup code)
421 * Please note that CFG_SDRAM_BASE _must_ start at 0
422 * Note also that the logic that sets CFG_RAMBOOT is platform dependent.
424 #define CFG_MONITOR_BASE CFG_FLASH0_BASE
426 #ifndef CFG_MONITOR_BASE
427 #define CFG_MONITOR_BASE 0x0ff80000
430 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
434 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 374 kB for Monitor */
435 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
438 * For booting Linux, the board info and command line data
439 * have to be in the first 8 MB of memory, since this is
440 * the maximum mapped by the Linux kernel during initialization.
442 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
444 /*-----------------------------------------------------------------------
445 * FLASH and environment organization
448 #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
449 #define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
450 #define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
451 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
452 #define CFG_FLASH_INCREMENT 0 /* there is only one bank */
453 #define CFG_FLASH_PROTECTION 1 /* use hardware protection */
454 #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
459 # define CFG_ENV_IS_IN_FLASH 1
460 # ifdef CFG_ENV_IN_OWN_SECT
461 # define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
462 # define CFG_ENV_SECT_SIZE 0x40000
464 # define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE)
465 # define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
466 # define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sect real size */
467 # endif /* CFG_ENV_IN_OWN_SECT */
470 # define CFG_ENV_IS_IN_FLASH 1
471 # define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x40000)
472 #define CFG_ENV_SIZE 0x1000
473 # define CFG_ENV_SECT_SIZE 0x40000
474 #endif /* CFG_RAMBOOT */
476 /*-----------------------------------------------------------------------
477 * Cache Configuration
479 #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
481 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
482 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
485 /*-----------------------------------------------------------------------
486 * HIDx - Hardware Implementation-dependent Registers 2-11
487 *-----------------------------------------------------------------------
488 * HID0 also contains cache control - initially enable both caches and
489 * invalidate contents, then the final state leaves only the instruction
490 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
491 * but Soft reset does not.
493 * HID1 has only read-only information - nothing to set.
495 #define CFG_HID0_INIT (HID0_ICE |\
502 #define CFG_HID0_FINAL (HID0_ICE |\
508 /*-----------------------------------------------------------------------
509 * RMR - Reset Mode Register
510 *-----------------------------------------------------------------------
514 /*-----------------------------------------------------------------------
515 * BCR - Bus Configuration 4-25
516 *-----------------------------------------------------------------------
518 #define CFG_BCR (BCR_EBM |\
521 /*-----------------------------------------------------------------------
522 * SIUMCR - SIU Module Configuration 4-31
523 * Ref Section 4.3.2.6 page 4-31
524 *-----------------------------------------------------------------------
527 #define CFG_SIUMCR (SIUMCR_ESE |\
537 /*-----------------------------------------------------------------------
538 * SYPCR - System Protection Control 11-9
539 * SYPCR can only be written once after reset!
540 *-----------------------------------------------------------------------
541 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
543 #define CFG_SYPCR (SYPCR_SWTC |\
550 /*-----------------------------------------------------------------------
551 * TMCNTSC - Time Counter Status and Control 4-40
552 *-----------------------------------------------------------------------
553 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
554 * and enable Time Counter
556 #define CFG_TMCNTSC (TMCNTSC_SEC |\
561 /*-----------------------------------------------------------------------
562 * PISCR - Periodic Interrupt Status and Control 4-42
563 *-----------------------------------------------------------------------
564 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
567 #define CFG_PISCR (PISCR_PS |\
571 /*-----------------------------------------------------------------------
572 * SCCR - System Clock Control 9-8
573 *-----------------------------------------------------------------------
577 /*-----------------------------------------------------------------------
578 * RCCR - RISC Controller Configuration 13-7
579 *-----------------------------------------------------------------------
584 * Initialize Memory Controller:
586 * Bank Bus Machine PortSz Device
587 * ---- --- ------- ------ ------
588 * 0 60x GPCM 32 bit FLASH (SIMM - 32MB) *
590 * 2 60x SDRAM 64 bit SDRAM (DIMM - 128MB)
591 * 3 60x SDRAM 64 bit SDRAM (DIMM - 128MB)
592 * 4 Local SDRAM 32 bit SDRAM (on board - 16MB)
593 * 5 60x GPCM 8 bit Mailbox/EEPROM (8KB)
594 * 6 60x GPCM 8 bit FLASH (on board - 2MB) *
595 * 7 60x GPCM 8 bit LEDs, switches
597 * (*) This configuration requires the PPMC8260 be configured
598 * so that *CS0 goes to the FLASH SIMM, and *CS6 goes to
599 * the on board FLASH. In other words, JP24 should have
600 * pins 1 and 2 jumpered and pins 3 and 4 jumpered.
604 /*-----------------------------------------------------------------------
605 * BR0,BR1 - Base Register
606 * Ref: Section 10.3.1 on page 10-14
607 * OR0,OR1 - Option Register
608 * Ref: Section 10.3.2 on page 10-18
609 *-----------------------------------------------------------------------
612 /* Bank 0,1 - FLASH SIMM
614 * This expects the FLASH SIMM to be connected to *CS0
615 * It consists of 4 AM29F080B parts.
617 * Note: For the 4 MB SIMM, *CS1 is unused.
620 /* BR0 is configured as follows:
622 * - Base address of 0xFE000000
624 * - Data errors checking is disabled
625 * - Read and write access
627 * - Access are handled by the memory controller according to MSEL
628 * - Not used for atomic operations
629 * - No data pipelining is done
632 #define CFG_BR0_PRELIM ((CFG_FLASH0_BASE & BRx_BA_MSK) |\
637 /* OR0 is configured as follows:
640 * - *BCTL0 is asserted upon access to the current memory bank
641 * - *CW / *WE are negated a quarter of a clock earlier
642 * - *CS is output at the same time as the address lines
643 * - Uses a clock cycle length of 5
644 * - *PSDVAL is generated internally by the memory controller
645 * unless *GTA is asserted earlier externally.
646 * - Relaxed timing is generated by the GPCM for accesses
647 * initiated to this memory region.
648 * - One idle clock is inserted between a read access from the
649 * current bank and the next access.
651 #define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH0_SIZE) |\
658 /*-----------------------------------------------------------------------
659 * BR2,BR3 - Base Register
660 * Ref: Section 10.3.1 on page 10-14
661 * OR2,OR3 - Option Register
662 * Ref: Section 10.3.2 on page 10-16
663 *-----------------------------------------------------------------------
667 * Bank 2,3 - 128 MB SDRAM DIMM
670 /* With a 128 MB DIMM, the BR2 is configured as follows:
672 * - Base address of 0x00000000/0x08000000
673 * - 64 bit port size (60x bus only)
674 * - Data errors checking is disabled
675 * - Read and write access
677 * - Access are handled by the memory controller according to MSEL
678 * - Not used for atomic operations
679 * - No data pipelining is done
682 #define CFG_BR2_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
687 #define CFG_BR3_PRELIM ((CFG_SDRAM1_BASE & BRx_BA_MSK) |\
692 /* With a 128 MB DIMM, the OR2 is configured as follows:
695 * - 4 internal banks per device
696 * - Row start address bit is A8 with PSDMR[PBI] = 0
697 * - 13 row address lines
698 * - Back-to-back page mode
699 * - Internal bank interleaving within save device enabled
702 #define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\
704 ORxS_ROWST_PBI0_A7 |\
707 #define CFG_OR3_PRELIM (MEG_TO_AM(CFG_SDRAM1_SIZE) |\
709 ORxS_ROWST_PBI0_A7 |\
713 /*-----------------------------------------------------------------------
714 * PSDMR - 60x Bus SDRAM Mode Register
715 * Ref: Section 10.3.3 on page 10-21
716 *-----------------------------------------------------------------------
719 /* With a 128 MB DIMM, the PSDMR is configured as follows:
721 * - Page Based Interleaving,
724 * - Address Multiplexing where A5 is output on A14 pin
725 * (A6 on A15, and so on),
726 * - use address pins A13-A15 as bank select,
727 * - A9 is output on SDA10 during an ACTIVATE command,
728 * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
729 * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
731 * - earliest timing for READ/WRITE command after ACTIVATE command is
733 * - earliest timing for PRECHARGE after last data was read is 1 clock,
734 * - earliest timing for PRECHARGE after last data was written is 1 clock,
735 * - External Address Multiplexing enabled
736 * - CAS Latency is 2.
738 #define CFG_PSDMR (PSDMR_RFEN |\
739 PSDMR_SDAM_A14_IS_A5 |\
740 PSDMR_BSMA_A13_A15 |\
741 PSDMR_SDA10_PBI0_A9 |\
751 #define CFG_PSRT 0x0e
752 #define CFG_MPTPR MPTPR_PTP_DIV32
755 /*-----------------------------------------------------------------------
756 * BR4 - Base Register
757 * Ref: Section 10.3.1 on page 10-14
758 * OR4 - Option Register
759 * Ref: Section 10.3.2 on page 10-16
760 *-----------------------------------------------------------------------
764 * Bank 4 - On board SDRAM
767 /* With 16 MB of onboard SDRAM BR4 is configured as follows
769 * - Base address 0x38000000
771 * - Data error checking disabled
772 * - Read/Write access
774 * - Not used for atomic operations
775 * - No data pipelining is done
780 #define CFG_BR4_PRELIM ((CFG_SDRAM2_BASE & BRx_BA_MSK) |\
787 * With 16MB SDRAM, OR4 is configured as follows
788 * - 4 internal banks per device
789 * - Row start address bit is A10 with LSDMR[PBI] = 0
790 * - 12 row address lines
791 * - Back-to-back page mode
792 * - Internal bank interleaving within save device enabled
795 #define CFG_OR4_PRELIM (MEG_TO_AM(CFG_SDRAM2_SIZE) |\
797 ORxS_ROWST_PBI0_A10 |\
801 /*-----------------------------------------------------------------------
802 * LSDMR - Local Bus SDRAM Mode Register
803 * Ref: Section 10.3.4 on page 10-24
804 *-----------------------------------------------------------------------
807 /* With a 16 MB onboard SDRAM, the LSDMR is configured as follows:
809 * - Page Based Interleaving,
812 * - Address Multiplexing where A5 is output on A13 pin
813 * (A6 on A15, and so on),
814 * - use address pins A15-A17 as bank select,
815 * - A11 is output on SDA10 during an ACTIVATE command,
816 * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
817 * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
819 * - earliest timing for READ/WRITE command after ACTIVATE command is
821 * - SDRAM burst length is 8
822 * - earliest timing for PRECHARGE after last data was read is 1 clock,
823 * - earliest timing for PRECHARGE after last data was written is 1 clock,
824 * - External Address Multiplexing disabled
825 * - CAS Latency is 2.
827 #define CFG_LSDMR (PSDMR_RFEN |\
828 PSDMR_SDAM_A13_IS_A5 |\
829 PSDMR_BSMA_A15_A17 |\
830 PSDMR_SDA10_PBI0_A11 |\
839 #define CFG_LSRT 0x0e
841 /*-----------------------------------------------------------------------
842 * BR5 - Base Register
843 * Ref: Section 10.3.1 on page 10-14
844 * OR5 - Option Register
845 * Ref: Section 10.3.2 on page 10-16
846 *-----------------------------------------------------------------------
850 * Bank 5 EEProm and Mailbox
852 * The EEPROM and mailbox live on the same chip select.
853 * the eeprom is selected if the MSb of the address is set and the mailbox is
854 * selected if the MSb of the address is clear.
858 /* BR5 is configured as follows:
860 * - Base address of 0x32000000/0xF2000000
862 * - Data error checking disabled
863 * - Read/Write access
866 * - No data pipelining is done
870 #define CFG_BR5_PRELIM ((CFG_MAILBOX_BASE & BRx_BA_MSK) |\
875 /* OR5 is configured as follows
876 * - buffer control enabled
877 * - chip select negated normally
878 * - CS output 1/2 clock after address
880 * - *PSDVAL is generated internally by the memory controller
881 * unless *GTA is asserted earlier externally.
882 * - Relaxed timing is generated by the GPCM for accesses
883 * initiated to this memory region.
884 * - One idle clock is inserted between a read access from the
885 * current bank and the next access.
888 #define CFG_OR5_PRELIM ((P2SZ_TO_AM(CFG_MAILBOX_SIZE) & ~0x80000000) |\
894 /*-----------------------------------------------------------------------
895 * BR6 - Base Register
896 * Ref: Section 10.3.1 on page 10-14
897 * OR6 - Option Register
898 * Ref: Section 10.3.2 on page 10-18
899 *-----------------------------------------------------------------------
902 /* Bank 6 - I/O select
906 /* BR6 is configured as follows:
908 * - Base address of 0xE0000000
910 * - Data errors checking is disabled
911 * - Read and write access
913 * - Access are handled by the memory controller according to MSEL
914 * - Not used for atomic operations
915 * - No data pipelining is done
918 #define CFG_BR6_PRELIM ((CFG_IOSELECT_BASE & BRx_BA_MSK) |\
923 /* OR6 is configured as follows
924 * - buffer control enabled
925 * - chip select negated normally
926 * - CS output 1/2 clock after address
928 * - *PSDVAL is generated internally by the memory controller
929 * unless *GTA is asserted earlier externally.
930 * - Relaxed timing is generated by the GPCM for accesses
931 * initiated to this memory region.
932 * - One idle clock is inserted between a read access from the
933 * current bank and the next access.
936 #define CFG_OR6_PRELIM (MEG_TO_AM(CFG_IOSELECT_SIZE) |\
943 /*-----------------------------------------------------------------------
944 * BR7 - Base Register
945 * Ref: Section 10.3.1 on page 10-14
946 * OR7 - Option Register
947 * Ref: Section 10.3.2 on page 10-18
948 *-----------------------------------------------------------------------
951 /* Bank 7 - LEDs and switches
953 * LEDs are at 0x00001 (write only)
954 * switches are at 0x00001 (read only)
958 /* BR7 is configured as follows:
960 * - Base address of 0xA0000000
962 * - Data errors checking is disabled
963 * - Read and write access
965 * - Access are handled by the memory controller according to MSEL
966 * - Not used for atomic operations
967 * - No data pipelining is done
970 #define CFG_BR7_PRELIM ((CFG_LED_BASE & BRx_BA_MSK) |\
976 /* OR7 is configured as follows:
979 * - *BCTL0 is asserted upon access to the current memory bank
980 * - *CW / *WE are negated a quarter of a clock earlier
981 * - *CS is output at the same time as the address lines
982 * - Uses a clock cycle length of 15
983 * - *PSDVAL is generated internally by the memory controller
984 * unless *GTA is asserted earlier externally.
985 * - Relaxed timing is generated by the GPCM for accesses
986 * initiated to this memory region.
987 * - One idle clock is inserted between a read access from the
988 * current bank and the next access.
990 #define CFG_OR7_PRELIM (ORxG_AM_MSK |\
996 #endif /* CFG_LED_BASE */
999 * Internal Definitions
1003 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
1004 #define BOOTFLAG_WARM 0x02 /* Software reboot */
1006 #endif /* __CONFIG_H */