5 * Wind River PPMC 7xx/74xx board configuration file.
7 * By Richard Danter (richard.danter@windriver.com)
8 * Copyright (C) 2005 Wind River Systems
15 #define CONFIG_PPMC7XX
18 /*===================================================================
20 * User configurable settings - Modify to your preference
22 *===================================================================
28 * DEBUG - Define this is you want extra debug info
29 * GTREGREAD - Required to build with debug
30 * do_bdinfo - Required to build with debug
34 #define GTREGREAD(x) 0xFFFFFFFF
35 #define do_bdinfo(a,b,c,d)
41 * CONFIG_7xx - We have a 750 or 755 CPU
42 * CONFIG_74xx - We have a 7400 CPU
43 * CONFIG_ALTIVEC - We have altivec enabled CPU (only 7400)
44 * CONFIG_BUS_CLK - System bus clock in Hz
50 #define CONFIG_BUS_CLK 66000000
52 #define CONFIG_SYS_TEXT_BASE 0xFFF00000
55 #include <galileo/core.h>
59 * Monitor configuration
61 * List of command sets to include in shell
63 * The following command sets have been tested and known to work:
65 * CMD_CACHE - Cache control commands
66 * CMD_MEMORY - Memory display, change and test commands
67 * CMD_FLASH - Erase and program flash
68 * CMD_ENV - Environment commands
69 * CMD_RUN - Run commands stored in env vars
70 * CMD_ELF - Load ELF files
71 * CMD_NET - Networking/file download commands
72 * CMD_PIN - ICMP Echo Request command
73 * CMD_PCI - PCI Bus scanning command
79 #define CONFIG_BOOTP_BOOTFILESIZE
80 #define CONFIG_BOOTP_BOOTPATH
81 #define CONFIG_BOOTP_GATEWAY
82 #define CONFIG_BOOTP_HOSTNAME
86 * Command line configuration.
88 #include <config_cmd_default.h>
90 #define CONFIG_CMD_FLASH
91 #define CONFIG_CMD_SAVEENV
92 #define CONFIG_CMD_RUN
93 #define CONFIG_CMD_ELF
94 #define CONFIG_CMD_NET
95 #define CONFIG_CMD_PING
96 #define CONFIG_CMD_PCI
98 #undef CONFIG_CMD_KGDB
102 * Serial configuration
104 * CONFIG_CONS_INDEX - Serial console port number (COM1)
105 * CONFIG_BAUDRATE - Serial speed
108 #define CONFIG_CONS_INDEX 1
109 #define CONFIG_BAUDRATE 9600
115 * CONFIG_PCI - Enable PCI bus
116 * CONFIG_PCI_PNP - Enable Plug & Play support
117 * CONFIG_PCI_SCAN_SHOW - Enable display of devices at startup
121 #define CONFIG_PCI_INDIRECT_BRIDGE
122 #define CONFIG_PCI_PNP
123 #undef CONFIG_PCI_SCAN_SHOW
129 * CONFIG_EEPRO100 - Intel 8255x Ethernet Controller
130 * CONFIG_EEPRO100_SROM_WRITE - Enable writing to network card ROM
133 #define CONFIG_EEPRO100
134 #define CONFIG_EEPRO100_SROM_WRITE
138 * Enable extra init functions
140 * CONFIG_MISC_INIT_F - Call pre-relocation init functions
141 * CONFIG_MISC_INIT_R - Call post relocation init functions
144 #undef CONFIG_MISC_INIT_F
145 #define CONFIG_MISC_INIT_R
151 * CONFIG_BOOTCOMMAND - Command(s) to execute to auto-boot
152 * CONFIG_BOOTDELAY - How long to wait before auto-boot (in sec)
155 #define CONFIG_BOOTCOMMAND \
157 "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
158 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
160 #define CONFIG_BOOTDELAY 5
163 /*===================================================================
165 * Board configuration settings - You should not need to modify these
167 *===================================================================
174 * This board runs in a standard CHRP (Map-B) configuration.
176 * Type Start End Size Width Chip Sel
177 * ----------- ----------- ----------- ------- ------- --------
178 * SDRAM 0x00000000 0x04000000 64MB 64b SDRAMCS0
179 * User LED's 0x78000000 RCS3
180 * UART 0x7C000000 RCS2
181 * Mailbox 0xFF000000 RCS1
182 * Flash 0xFFC00000 0xFFFFFFFF 4MB 64b RCS0
184 * Flash sectors are laid out as follows.
186 * Sector Start End Size Comments
187 * ------- ----------- ----------- ------- -----------
188 * 0 0xFFC00000 0xFFC3FFFF 256KB
189 * 1 0xFFC40000 0xFFC7FFFF 256KB
190 * 2 0xFFC80000 0xFFCBFFFF 256KB
191 * 3 0xFFCC0000 0xFFCFFFFF 256KB
192 * 4 0xFFD00000 0xFFD3FFFF 256KB
193 * 5 0xFFD40000 0xFFD7FFFF 256KB
194 * 6 0xFFD80000 0xFFDBFFFF 256KB
195 * 7 0xFFDC0000 0xFFDFFFFF 256KB
196 * 8 0xFFE00000 0xFFE3FFFF 256KB
197 * 9 0xFFE40000 0xFFE7FFFF 256KB
198 * 10 0xFFE80000 0xFFEBFFFF 256KB
199 * 11 0xFFEC0000 0xFFEFFFFF 256KB
200 * 12 0xFFF00000 0xFFF3FFFF 256KB U-Boot code here
201 * 13 0xFFF40000 0xFFF7FFFF 256KB
202 * 14 0xFFF80000 0xFFFBFFFF 256KB
203 * 15 0xFFFC0000 0xFFFDFFFF 128KB
204 * 16 0xFFFE0000 0xFFFE7FFF 32KB U-Boot env vars here
205 * 17 0xFFFE8000 0xFFFEFFFF 32KB U-Boot backup copy of env vars here
206 * 18 0xFFFF0000 0xFFFFFFFF 64KB
211 * SDRAM config - see memory map details above.
213 * CONFIG_SYS_SDRAM_BASE - Start address of SDRAM, this _must_ be zero!
214 * CONFIG_SYS_SDRAM_SIZE - Total size of contiguous SDRAM bank(s)
217 #define CONFIG_SYS_SDRAM_BASE 0x00000000
218 #define CONFIG_SYS_SDRAM_SIZE 0x04000000
222 * Flash config - see memory map details above.
224 * CONFIG_SYS_FLASH_BASE - Start address of flash memory
225 * CONFIG_SYS_FLASH_SIZE - Total size of contiguous flash mem
226 * CONFIG_SYS_FLASH_ERASE_TOUT - Erase timeout in ms
227 * CONFIG_SYS_FLASH_WRITE_TOUT - Write timeout in ms
228 * CONFIG_SYS_MAX_FLASH_BANKS - Number of banks of flash on board
229 * CONFIG_SYS_MAX_FLASH_SECT - Number of sectors in a bank
232 #define CONFIG_SYS_FLASH_BASE 0xFFC00000
233 #define CONFIG_SYS_FLASH_SIZE 0x00400000
234 #define CONFIG_SYS_FLASH_ERASE_TOUT 250000
235 #define CONFIG_SYS_FLASH_WRITE_TOUT 5000
236 #define CONFIG_SYS_MAX_FLASH_BANKS 1
237 #define CONFIG_SYS_MAX_FLASH_SECT 128
241 * Monitor config - see memory map details above
243 * CONFIG_SYS_MONITOR_BASE - Base address of monitor code
244 * CONFIG_SYS_MALLOC_LEN - Size of malloc pool (128KB)
247 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
248 #define CONFIG_SYS_MALLOC_LEN 0x20000
252 * Command shell settings
254 * CONFIG_SYS_BARGSIZE - Boot Argument buffer size
255 * CONFIG_SYS_BOOTMAPSZ - Size of app's mapped RAM at boot (Linux=8MB)
256 * CONFIG_SYS_CBSIZE - Console Buffer (input) size
257 * CONFIG_SYS_LOAD_ADDR - Default load address
258 * CONFIG_SYS_LONGHELP - Provide more detailed help
259 * CONFIG_SYS_MAXARGS - Number of args accepted by monitor commands
260 * CONFIG_SYS_MEMTEST_START - Start address of test to run on RAM
261 * CONFIG_SYS_MEMTEST_END - End address of RAM test
262 * CONFIG_SYS_PBSIZE - Print Buffer (output) size
263 * CONFIG_SYS_PROMPT - Prompt string
266 #define CONFIG_SYS_BARGSIZE 1024
267 #define CONFIG_SYS_BOOTMAPSZ 0x800000
268 #define CONFIG_SYS_CBSIZE 1024
269 #define CONFIG_SYS_LOAD_ADDR 0x100000
270 #define CONFIG_SYS_LONGHELP
271 #define CONFIG_SYS_MAXARGS 16
272 #define CONFIG_SYS_MEMTEST_START 0x00040000
273 #define CONFIG_SYS_MEMTEST_END 0x00040100
274 #define CONFIG_SYS_PBSIZE 1024
278 * Environment config - see memory map details above
280 * CONFIG_ENV_IS_IN_FLASH - The env variables are stored in flash
281 * CONFIG_ENV_ADDR - Address of the sector containing env vars
282 * CONFIG_ENV_SIZE - Ammount of RAM for env vars (used to save RAM, 4KB)
283 * CONFIG_ENV_SECT_SIZE - Size of sector containing env vars (32KB)
286 #define CONFIG_ENV_IS_IN_FLASH 1
287 #define CONFIG_ENV_ADDR 0xFFFE0000
288 #define CONFIG_ENV_SIZE 0x1000
289 #define CONFIG_ENV_ADDR_REDUND 0xFFFE8000
290 #define CONFIG_ENV_SIZE_REDUND 0x1000
291 #define CONFIG_ENV_SECT_SIZE 0x8000
297 * Since the main system RAM is initialised very early, we place the INIT_RAM
298 * in the main system RAM just above the exception vectors. The contents are
299 * copied to top of RAM by the init code.
301 * CONFIG_SYS_INIT_RAM_ADDR - Address of Init RAM, above exception vect
302 * CONFIG_SYS_INIT_RAM_SIZE - Size of Init RAM
303 * GENERATED_GBL_DATA_SIZE - Ammount of RAM to reserve for global data
304 * CONFIG_SYS_GBL_DATA_OFFSET - Start of global data, top of stack
307 #define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4000)
308 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000
309 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
315 * BAT0 - System SDRAM
316 * BAT1 - LED's and Serial Port
318 * BAT3 - PCI I/O including Flash Memory
321 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
322 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
323 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
324 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
326 #define CONFIG_SYS_IBAT1L (0x70000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
327 #define CONFIG_SYS_IBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
328 #define CONFIG_SYS_DBAT1L (0x70000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
329 #define CONFIG_SYS_DBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
331 #define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
332 #define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
333 #define CONFIG_SYS_DBAT2L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
334 #define CONFIG_SYS_DBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
336 #define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
337 #define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
338 #define CONFIG_SYS_DBAT3L (0xF0000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
339 #define CONFIG_SYS_DBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
345 * CONFIG_SYS_CACHELINE_SIZE - Size of a cache line (CPU specific)
346 * CONFIG_SYS_L2 - L2 cache enabled if defined
347 * L2_INIT - L2 cache init flags
348 * L2_ENABLE - L2 cache enable flags
351 #define CONFIG_SYS_CACHELINE_SIZE 32
360 * CONFIG_SYS_BUS_CLK - Bus clock frequency in Hz
361 * CONFIG_SYS_HZ - Decrementer freq in Hz
364 #define CONFIG_SYS_BUS_CLK CONFIG_BUS_CLK
370 * CONFIG_SYS_NS16550 - Include the NS16550 driver
371 * CONFIG_SYS_NS16550_SERIAL - Include the serial (wrapper) driver
372 * CONFIG_SYS_NS16550_CLK - Frequency of reference clock
373 * CONFIG_SYS_NS16550_REG_SIZE - 64-bit accesses to 8-bit port
374 * CONFIG_SYS_NS16550_COM1 - Base address of 1st serial port
377 #define CONFIG_SYS_NS16550
378 #define CONFIG_SYS_NS16550_SERIAL
379 #define CONFIG_SYS_NS16550_CLK 3686400
380 #define CONFIG_SYS_NS16550_REG_SIZE -8
381 #define CONFIG_SYS_NS16550_COM1 0x7C000000
385 * PCI Config - Address Map B (CHRP)
388 #define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
389 #define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
390 #define CONFIG_SYS_PCI_MEMORY_SIZE 0x40000000
391 #define CONFIG_SYS_PCI_MEM_BUS 0x80000000
392 #define CONFIG_SYS_PCI_MEM_PHYS 0x80000000
393 #define CONFIG_SYS_PCI_MEM_SIZE 0x7D000000
394 #define CONFIG_SYS_ISA_MEM_BUS 0x00000000
395 #define CONFIG_SYS_ISA_MEM_PHYS 0xFD000000
396 #define CONFIG_SYS_ISA_MEM_SIZE 0x01000000
397 #define CONFIG_SYS_PCI_IO_BUS 0x00800000
398 #define CONFIG_SYS_PCI_IO_PHYS 0xFE800000
399 #define CONFIG_SYS_PCI_IO_SIZE 0x00400000
400 #define CONFIG_SYS_ISA_IO_BUS 0x00000000
401 #define CONFIG_SYS_ISA_IO_PHYS 0xFE000000
402 #define CONFIG_SYS_ISA_IO_SIZE 0x00800000
403 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_ISA_IO_PHYS
404 #define CONFIG_SYS_ISA_IO CONFIG_SYS_ISA_IO_PHYS
405 #define CONFIG_SYS_60X_PCI_IO_OFFSET CONFIG_SYS_ISA_IO_PHYS
409 * Extra init functions
411 * CONFIG_SYS_BOARD_ASM_INIT - Call assembly init code
414 #define CONFIG_SYS_BOARD_ASM_INIT
416 #endif /* __CONFIG_H */