include/configs/pm9g45.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2010
   4  * Ilko Iliev <iliev@ronetix.at>
   5  * Asen Dimov <dimov@ronetix.at>
   6  * Ronetix GmbH <www.ronetix.at>
   7  *
   8  * (C) Copyright 2007-2008
   9  * Stelian Pop <stelian@popies.net>
  10  * Lead Tech Design <www.leadtechdesign.com>
  11  *
  12  * Configuation settings for the PM9G45 board.
  13  */
  14
  15 #ifndef __CONFIG_H
  16 #define __CONFIG_H
  17
  18 /* ARM asynchronous clock */
  19 #define CONFIG_SYS_AT91_SLOW_CLOCK      32768
  20 #define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
  21
  22 /* general purpose I/O */
  23 #define CONFIG_ATMEL_LEGACY             /* required until (g)pio is fixed */
  24
  25 /*
  26  * BOOTP options
  27  */
  28 #define CONFIG_BOOTP_BOOTFILESIZE
  29
  30 /* SDRAM */
  31 #define CONFIG_SYS_SDRAM_BASE           0x70000000
  32 #define CONFIG_SYS_SDRAM_SIZE           0x08000000
  33
  34 #define CONFIG_SYS_INIT_SP_ADDR \
  35         (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
  36
  37 /* NAND flash */
  38 #ifdef CONFIG_CMD_NAND
  39 #define CONFIG_SYS_MAX_NAND_DEVICE              1
  40 #define CONFIG_SYS_NAND_BASE                    ATMEL_BASE_CS3
  41 #define CONFIG_SYS_NAND_DBW_8
  42 /* our ALE is AD21 */
  43 #define CONFIG_SYS_NAND_MASK_ALE                BIT(21)
  44 /* our CLE is AD22 */
  45 #define CONFIG_SYS_NAND_MASK_CLE                BIT(22)
  46 #define CONFIG_SYS_NAND_ENABLE_PIN              AT91_PIN_PC14
  47 #define CONFIG_SYS_NAND_READY_PIN               AT91_PIN_PD3
  48 #define CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT
  49 #endif
  50
  51 /* Ethernet */
  52 #define CONFIG_RESET_PHY_R
  53 #define CONFIG_AT91_WANTS_COMMON_PHY
  54
  55 #ifdef CONFIG_NAND_BOOT
  56 /* bootstrap + u-boot + env in nandflash */
  57
  58 #define CONFIG_BOOTCOMMAND                                              \
  59         "nand read 0x70000000 0x200000 0x300000;"                       \
  60         "bootm 0x70000000"
  61 #elif CONFIG_SD_BOOT
  62 /* bootstrap + u-boot + env + linux in mmc */
  63
  64 #define CONFIG_BOOTCOMMAND      "fatload mmc 0:1 0x71000000 dtb; " \
  65                                 "fatload mmc 0:1 0x72000000 zImage; " \
  66                                 "bootz 0x72000000 - 0x71000000"
  67 #endif
  68
  69 /* Defines for SPL */
  70 #define CONFIG_SPL_MAX_SIZE             0x010000
  71 #define CONFIG_SPL_STACK                0x310000
  72
  73 #define CONFIG_SYS_MONITOR_LEN          0x80000
  74
  75 #ifdef CONFIG_SD_BOOT
  76
  77 #define CONFIG_SPL_BSS_START_ADDR       0x70000000
  78 #define CONFIG_SPL_BSS_MAX_SIZE         0x00080000
  79 #define CONFIG_SYS_SPL_MALLOC_START     0x70080000
  80 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x00080000
  81
  82 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot.img"
  83
  84 #elif CONFIG_NAND_BOOT
  85 #define CONFIG_SPL_NAND_SOFTECC
  86 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x40000
  87 #define CONFIG_SYS_NAND_U_BOOT_SIZE     0x80000
  88 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
  89
  90 #define CONFIG_SYS_NAND_PAGE_SIZE       0x800
  91 #define CONFIG_SYS_NAND_BLOCK_SIZE      0x20000
  92 #define CONFIG_SYS_NAND_PAGE_COUNT      64
  93 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
  94 #define CONFIG_SYS_NAND_ECCSIZE         256
  95 #define CONFIG_SYS_NAND_ECCBYTES        3
  96 #define CONFIG_SYS_NAND_OOBSIZE         64
  97 #define CONFIG_SYS_NAND_ECCPOS          { 40, 41, 42, 43, 44, 45, 46, 47, \
  98                                           48, 49, 50, 51, 52, 53, 54, 55, \
  99                                           56, 57, 58, 59, 60, 61, 62, 63, }
 100 #endif
 101
 102 #define CONFIG_SPL_ATMEL_SIZE
 103 #define CONFIG_SYS_MASTER_CLOCK         132096000
 104 #define CONFIG_SYS_AT91_PLLA            0x20c73f03
 105 #define CONFIG_SYS_MCKR                 0x1301
 106 #define CONFIG_SYS_MCKR_CSS             0x1302
 107
 108 #endif