include/configs/pm9g45.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2010
   4  * Ilko Iliev <iliev@ronetix.at>
   5  * Asen Dimov <dimov@ronetix.at>
   6  * Ronetix GmbH <www.ronetix.at>
   7  *
   8  * (C) Copyright 2007-2008
   9  * Stelian Pop <stelian@popies.net>
  10  * Lead Tech Design <www.leadtechdesign.com>
  11  *
  12  * Configuation settings for the PM9G45 board.
  13  */
  14
  15 #ifndef __CONFIG_H
  16 #define __CONFIG_H
  17
  18 /* ARM asynchronous clock */
  19 #define CONFIG_SYS_AT91_SLOW_CLOCK      32768
  20 #define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
  21
  22 #define CONFIG_CMDLINE_TAG              /* enable passing of ATAGs      */
  23 #define CONFIG_SETUP_MEMORY_TAGS
  24 #define CONFIG_INITRD_TAG
  25 #define CONFIG_SKIP_LOWLEVEL_INIT
  26
  27 /* general purpose I/O */
  28 #define CONFIG_ATMEL_LEGACY             /* required until (g)pio is fixed */
  29
  30 /*
  31  * BOOTP options
  32  */
  33 #define CONFIG_BOOTP_BOOTFILESIZE
  34
  35 /* SDRAM */
  36 #define CONFIG_SYS_SDRAM_BASE           0x70000000
  37 #define CONFIG_SYS_SDRAM_SIZE           0x08000000
  38
  39 #define CONFIG_SYS_INIT_SP_ADDR \
  40         (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
  41
  42 /* NAND flash */
  43 #ifdef CONFIG_CMD_NAND
  44 #define CONFIG_SYS_MAX_NAND_DEVICE              1
  45 #define CONFIG_SYS_NAND_BASE                    ATMEL_BASE_CS3
  46 #define CONFIG_SYS_NAND_DBW_8
  47 /* our ALE is AD21 */
  48 #define CONFIG_SYS_NAND_MASK_ALE                BIT(21)
  49 /* our CLE is AD22 */
  50 #define CONFIG_SYS_NAND_MASK_CLE                BIT(22)
  51 #define CONFIG_SYS_NAND_ENABLE_PIN              AT91_PIN_PC14
  52 #define CONFIG_SYS_NAND_READY_PIN               AT91_PIN_PD3
  53 #define CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT
  54 #endif
  55
  56 /* Ethernet */
  57 #define CONFIG_RESET_PHY_R
  58 #define CONFIG_AT91_WANTS_COMMON_PHY
  59
  60 #ifdef CONFIG_NAND_BOOT
  61 /* bootstrap + u-boot + env in nandflash */
  62
  63 #define CONFIG_BOOTCOMMAND                                              \
  64         "nand read 0x70000000 0x200000 0x300000;"                       \
  65         "bootm 0x70000000"
  66 #elif CONFIG_SD_BOOT
  67 /* bootstrap + u-boot + env + linux in mmc */
  68
  69 #define CONFIG_BOOTCOMMAND      "fatload mmc 0:1 0x71000000 dtb; " \
  70                                 "fatload mmc 0:1 0x72000000 zImage; " \
  71                                 "bootz 0x72000000 - 0x71000000"
  72 #endif
  73
  74 /*
  75  * Size of malloc() pool
  76  */
  77 #define CONFIG_SYS_MALLOC_LEN           ROUND(3 * CONFIG_ENV_SIZE + \
  78                                               128 * 1024, 0x1000)
  79
  80 /* Defines for SPL */
  81 #define CONFIG_SPL_MAX_SIZE             0x010000
  82 #define CONFIG_SPL_STACK                0x310000
  83
  84 #define CONFIG_SYS_MONITOR_LEN          0x80000
  85
  86 #ifdef CONFIG_SD_BOOT
  87
  88 #define CONFIG_SPL_BSS_START_ADDR       0x70000000
  89 #define CONFIG_SPL_BSS_MAX_SIZE         0x00080000
  90 #define CONFIG_SYS_SPL_MALLOC_START     0x70080000
  91 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x00080000
  92
  93 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot.img"
  94
  95 #elif CONFIG_NAND_BOOT
  96 #define CONFIG_SPL_NAND_SOFTECC
  97 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x40000
  98 #define CONFIG_SYS_NAND_U_BOOT_SIZE     0x80000
  99 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 100
 101 #define CONFIG_SYS_NAND_PAGE_SIZE       0x800
 102 #define CONFIG_SYS_NAND_BLOCK_SIZE      0x20000
 103 #define CONFIG_SYS_NAND_PAGE_COUNT      64
 104 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
 105 #define CONFIG_SYS_NAND_ECCSIZE         256
 106 #define CONFIG_SYS_NAND_ECCBYTES        3
 107 #define CONFIG_SYS_NAND_OOBSIZE         64
 108 #define CONFIG_SYS_NAND_ECCPOS          { 40, 41, 42, 43, 44, 45, 46, 47, \
 109                                           48, 49, 50, 51, 52, 53, 54, 55, \
 110                                           56, 57, 58, 59, 60, 61, 62, 63, }
 111 #endif
 112
 113 #define CONFIG_SPL_ATMEL_SIZE
 114 #define CONFIG_SYS_MASTER_CLOCK         132096000
 115 #define CONFIG_SYS_AT91_PLLA            0x20c73f03
 116 #define CONFIG_SYS_MCKR                 0x1301
 117 #define CONFIG_SYS_MCKR_CSS             0x1302
 118
 119 #endif