include/configs/pm9g45.h

   1 /*
   2  * (C) Copyright 2010
   3  * Ilko Iliev <iliev@ronetix.at>
   4  * Asen Dimov <dimov@ronetix.at>
   5  * Ronetix GmbH <www.ronetix.at>
   6  *
   7  * (C) Copyright 2007-2008
   8  * Stelian Pop <stelian@popies.net>
   9  * Lead Tech Design <www.leadtechdesign.com>
  10  *
  11  * Configuation settings for the PM9G45 board.
  12  *
  13  * SPDX-License-Identifier:     GPL-2.0+
  14  */
  15
  16 #ifndef __CONFIG_H
  17 #define __CONFIG_H
  18
  19 /*
  20  * SoC must be defined first, before hardware.h is included.
  21  * In this case SoC is defined in boards.cfg.
  22  */
  23 #include <asm/hardware.h>
  24
  25
  26 #define CONFIG_PM9G45           1       /* It's an Ronetix PM9G45 */
  27 #define CONFIG_SYS_AT91_CPU_NAME        "AT91SAM9G45"
  28
  29 #define MACH_TYPE_PM9G45        2672
  30 #define CONFIG_MACH_TYPE        MACH_TYPE_PM9G45
  31
  32 /* ARM asynchronous clock */
  33 #define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
  34 #define CONFIG_SYS_AT91_SLOW_CLOCK      32768           /* slow clock xtal */
  35 #define CONFIG_SYS_TEXT_BASE            0x73f00000
  36
  37 #define CONFIG_ARCH_CPU_INIT
  38
  39 #define CONFIG_CMDLINE_TAG      1       /* enable passing of ATAGs */
  40 #define CONFIG_SETUP_MEMORY_TAGS 1
  41 #define CONFIG_INITRD_TAG       1
  42
  43 #define CONFIG_SKIP_LOWLEVEL_INIT
  44 #define CONFIG_BOARD_EARLY_INIT_F
  45
  46 /*
  47  * Hardware drivers
  48  */
  49 #define CONFIG_AT91_GPIO        1
  50 #define CONFIG_ATMEL_USART      1
  51 #define CONFIG_USART_BASE               ATMEL_BASE_DBGU
  52 #define CONFIG_USART_ID                 ATMEL_ID_SYS
  53
  54 #define CONFIG_SYS_USE_NANDFLASH        1
  55
  56 /* LED */
  57 #define CONFIG_AT91_LED
  58 #define CONFIG_RED_LED          GPIO_PIN_PD(31) /* this is the user1 led */
  59 #define CONFIG_GREEN_LED        GPIO_PIN_PD(0)  /* this is the user2 led */
  60
  61 #define CONFIG_BOOTDELAY        3
  62
  63 /*
  64  * BOOTP options
  65  */
  66 #define CONFIG_BOOTP_BOOTFILESIZE       1
  67 #define CONFIG_BOOTP_BOOTPATH           1
  68 #define CONFIG_BOOTP_GATEWAY            1
  69 #define CONFIG_BOOTP_HOSTNAME           1
  70
  71 /*
  72  * Command line configuration.
  73  */
  74 #define CONFIG_CMD_CACHE
  75 #define CONFIG_CMD_PING         1
  76 #define CONFIG_CMD_DHCP         1
  77 #define CONFIG_CMD_NAND         1
  78 #define CONFIG_CMD_USB          1
  79
  80 #define CONFIG_CMD_JFFS2                1
  81 #define CONFIG_JFFS2_CMDLINE            1
  82 #define CONFIG_JFFS2_NAND               1
  83 #define CONFIG_JFFS2_DEV                "nand0" /* NAND dev jffs2 lives on */
  84 #define CONFIG_JFFS2_PART_OFFSET        0       /* start of jffs2 partition */
  85 #define CONFIG_JFFS2_PART_SIZE          (256 * 1024 * 1024) /* partition */
  86
  87 /* SDRAM */
  88 #define CONFIG_NR_DRAM_BANKS            1
  89 #define PHYS_SDRAM                      0x70000000
  90 #define PHYS_SDRAM_SIZE                 0x08000000      /* 128 megs */
  91
  92 /* NOR flash, not available */
  93 #define CONFIG_SYS_NO_FLASH             1
  94
  95 /* NAND flash */
  96 #ifdef CONFIG_CMD_NAND
  97 #define CONFIG_NAND_ATMEL
  98 #define CONFIG_SYS_MAX_NAND_DEVICE      1
  99 #define CONFIG_SYS_NAND_BASE            0x40000000
 100 #define CONFIG_SYS_NAND_DBW_8           1
 101 /* our ALE is AD21 */
 102 #define CONFIG_SYS_NAND_MASK_ALE        (1 << 21)
 103 /* our CLE is AD22 */
 104 #define CONFIG_SYS_NAND_MASK_CLE        (1 << 22)
 105 #define CONFIG_SYS_NAND_ENABLE_PIN      GPIO_PIN_PC(14)
 106 #define CONFIG_SYS_NAND_READY_PIN       GPIO_PIN_PD(3)
 107
 108 #endif
 109
 110 /* Ethernet */
 111 #define CONFIG_MACB                     1
 112 #define CONFIG_RMII                     1
 113 #define CONFIG_NET_RETRY_COUNT          20
 114 #define CONFIG_RESET_PHY_R              1
 115
 116 /* USB */
 117 #define CONFIG_USB_ATMEL
 118 #define CONFIG_USB_ATMEL_CLK_SEL_UPLL
 119 #define CONFIG_USB_OHCI_NEW             1
 120 #define CONFIG_DOS_PARTITION            1
 121 #define CONFIG_SYS_USB_OHCI_CPU_INIT    1
 122 #define CONFIG_SYS_USB_OHCI_REGS_BASE   0x00700000 /* _UHP_OHCI_BASE */
 123 #define CONFIG_SYS_USB_OHCI_SLOT_NAME   "at91sam9g45"
 124 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      2
 125 #define CONFIG_USB_STORAGE              1
 126
 127 /* board specific(not enough SRAM) */
 128 #define CONFIG_AT91SAM9G45_LCD_BASE     PHYS_SDRAM + 0xE00000
 129
 130 #define CONFIG_SYS_LOAD_ADDR            PHYS_SDRAM + 0x2000000 /* load addr */
 131
 132 #define CONFIG_SYS_MEMTEST_START        PHYS_SDRAM
 133 #define CONFIG_SYS_MEMTEST_END          CONFIG_AT91SAM9G45_LCD_BASE
 134
 135 /* bootstrap + u-boot + env + linux in nandflash */
 136 #define CONFIG_ENV_IS_IN_NAND           1
 137 #define CONFIG_ENV_OFFSET               0x60000
 138 #define CONFIG_ENV_OFFSET_REDUND        0x80000
 139 #define CONFIG_ENV_SIZE                 0x20000         /* 1 sector = 128 kB */
 140 #define CONFIG_BOOTCOMMAND      "nand read 0x72000000 0x200000 0x200000; bootm"
 141 #define CONFIG_BOOTARGS         "fbcon=rotate:3 console=tty0 " \
 142                                 "console=ttyS0,115200 " \
 143                                 "root=/dev/mtdblock4 " \
 144                                 "mtdparts=atmel_nand:128k(bootstrap)ro," \
 145                                 "256k(uboot)ro,1664k(env)," \
 146                                 "2M(linux)ro,-(root) rw " \
 147                                 "rootfstype=jffs2"
 148
 149 #define CONFIG_BAUDRATE                 115200
 150
 151 #define CONFIG_SYS_CBSIZE               256
 152 #define CONFIG_SYS_MAXARGS              16
 153 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 154                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 155 #define CONFIG_SYS_LONGHELP             1
 156 #define CONFIG_CMDLINE_EDITING          1
 157 #define CONFIG_AUTO_COMPLETE
 158 #define CONFIG_SYS_HUSH_PARSER
 159
 160 /*
 161  * Size of malloc() pool
 162  */
 163 #define CONFIG_SYS_MALLOC_LEN           ROUND(3 * CONFIG_ENV_SIZE + 128*1024,\
 164                                         0x1000)
 165
 166 #define CONFIG_SYS_SDRAM_BASE   PHYS_SDRAM
 167 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
 168                                 GENERATED_GBL_DATA_SIZE)
 169
 170 #endif