2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian.pop@leadtechdesign.com>
4 * Lead Tech Design <www.leadtechdesign.com>
5 * Ilko Iliev <www.ronetix.at>
7 * Configuation settings for the RONETIX PM9263 board.
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 /* ARM asynchronous clock */
32 #define AT91_CPU_NAME "AT91SAM9263"
34 #define CONFIG_DISPLAY_BOARDINFO
36 #define MASTER_PLL_DIV 15
37 #define MASTER_PLL_MUL 162
38 #define MAIN_PLL_DIV 2 /* 2 or 4 */
39 #define AT91_MAIN_CLOCK 18432000
41 #define CONFIG_SYS_HZ 1000
43 #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
44 #define CONFIG_AT91SAM9263 1 /* It's an Atmel AT91SAM9263 SoC*/
45 #define CONFIG_PM9263 1 /* on a Ronetix PM9263 Board */
46 #define CONFIG_ARCH_CPU_INIT
47 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
50 #define CONFIG_SYS_MOR_VAL 0x00002001 /* CKGR_MOR - enable main osc. */
51 #define CONFIG_SYS_PLLAR_VAL \
52 (0x2000BF00 | ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
54 #if (MAIN_PLL_DIV == 2)
55 /* PCK/2 = MCK Master Clock from PLLA */
56 #define CONFIG_SYS_MCKR1_VAL 0x00000100
57 /* PCK/2 = MCK Master Clock from PLLA */
58 #define CONFIG_SYS_MCKR2_VAL 0x00000102
60 /* PCK/4 = MCK Master Clock from PLLA */
61 #define CONFIG_SYS_MCKR1_VAL 0x00000200
62 /* PCK/4 = MCK Master Clock from PLLA */
63 #define CONFIG_SYS_MCKR2_VAL 0x00000202
65 /* define PDC[31:16] as DATA[31:16] */
66 #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
67 /* no pull-up for D[31:16] */
68 #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
69 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
70 #define CONFIG_SYS_MATRIX_EBI0CSA_VAL 0x0001010A
71 /* EBI1_CSA, 3.3v, no pull-ups */
72 #define CONFIG_SYS_MATRIX_EBI1CSA_VAL 0x00010100
75 /* SDRAMC_MR Mode register */
76 #define CONFIG_SYS_SDRC_MR_VAL1 0
77 /* SDRAMC_TR - Refresh Timer register */
78 #define CONFIG_SYS_SDRC_TR_VAL1 0x13C
79 #define CONFIG_SYS_SDRC_CR_VAL 0x85227279 /*CL3*/
80 /* Memory Device Register -> SDRAM */
81 #define CONFIG_SYS_SDRC_MDR_VAL 0
82 #define CONFIG_SYS_SDRC_MR_VAL2 0x00000002 /* SDRAMC_MR */
83 #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
84 #define CONFIG_SYS_SDRC_MR_VAL3 4 /* SDRC_MR */
85 #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
86 #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
87 #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
88 #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
89 #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
90 #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
91 #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
92 #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
93 #define CONFIG_SYS_SDRC_MR_VAL4 3 /* SDRC_MR */
94 #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
95 #define CONFIG_SYS_SDRC_MR_VAL5 0 /* SDRC_MR */
96 #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
97 #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
98 #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
100 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
101 #define CONFIG_SYS_SMC0_SETUP0_VAL 0x0A0A0A0A /* SMC_SETUP */
102 #define CONFIG_SYS_SMC0_PULSE0_VAL 0x0B0B0B0B /* SMC_PULSE */
103 #define CONFIG_SYS_SMC0_CYCLE0_VAL 0x00160016 /* SMC_CYCLE */
104 #define CONFIG_SYS_SMC0_CTRL0_VAL 0x00161003 /* SMC_MODE */
106 /* setup SMC1, CS0 (PSRAM) - 16-bit */
107 #define CONFIG_SYS_SMC1_SETUP0_VAL 0x00000000 /* SMC_SETUP */
108 #define CONFIG_SYS_SMC1_PULSE0_VAL 0x07020707 /* SMC_PULSE */
109 #define CONFIG_SYS_SMC1_CYCLE0_VAL 0x00080008 /* SMC_CYCLE */
110 #define CONFIG_SYS_SMC1_CTRL0_VAL 0x31001000 /* SMC_MODE */
112 #define CONFIG_SYS_RSTC_RMR_VAL 0xA5000301 /* user reset enable */
115 #define CONFIG_SYS_WDTC_WDMR_VAL 0x3fff8fff /* disable watchdog */
119 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
120 #define CONFIG_SETUP_MEMORY_TAGS 1
121 #define CONFIG_INITRD_TAG 1
123 #undef CONFIG_SKIP_LOWLEVEL_INIT
124 #undef CONFIG_SKIP_RELOCATE_UBOOT
125 #define CONFIG_USER_LOWLEVEL_INIT 1
130 #define CONFIG_ATMEL_USART 1
134 #define CONFIG_USART3 1 /* USART 3 is DBGU */
138 #define LCD_BPP LCD_COLOR8
139 #define CONFIG_LCD_LOGO 1
140 #undef LCD_TEST_PATTERN
141 #define CONFIG_LCD_INFO 1
142 #define CONFIG_LCD_INFO_BELOW_LOGO 1
143 #define CONFIG_SYS_WHITE_ON_BLACK 1
144 #define CONFIG_ATMEL_LCD 1
145 #define CONFIG_ATMEL_LCD_BGR555 1
146 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
148 #define CONFIG_LCD_IN_PSRAM 1
151 #define CONFIG_AT91_LED
152 #define CONFIG_RED_LED AT91_PIN_PB7 /* this is the power led */
153 #define CONFIG_GREEN_LED AT91_PIN_PB8 /* this is the user1 led */
155 #define CONFIG_BOOTDELAY 3
160 #define CONFIG_BOOTP_BOOTFILESIZE 1
161 #define CONFIG_BOOTP_BOOTPATH 1
162 #define CONFIG_BOOTP_GATEWAY 1
163 #define CONFIG_BOOTP_HOSTNAME 1
166 * Command line configuration.
168 #include <config_cmd_default.h>
169 #undef CONFIG_CMD_BDI
170 #undef CONFIG_CMD_IMI
171 #undef CONFIG_CMD_AUTOSCRIPT
172 #undef CONFIG_CMD_FPGA
173 #undef CONFIG_CMD_LOADS
174 #undef CONFIG_CMD_IMLS
176 #define CONFIG_CMD_PING 1
177 #define CONFIG_CMD_DHCP 1
178 #define CONFIG_CMD_NAND 1
179 #define CONFIG_CMD_USB 1
182 #define CONFIG_NR_DRAM_BANKS 1
183 #define PHYS_SDRAM 0x20000000
184 #define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
187 #define CONFIG_ATMEL_DATAFLASH_SPI
188 #define CONFIG_HAS_DATAFLASH 1
189 #define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ)
190 #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
191 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
192 #define AT91_SPI_CLK 15000000
193 #define DATAFLASH_TCSS (0x1a << 16)
194 #define DATAFLASH_TCHS (0x1 << 24)
196 /* NOR flash, if populated */
197 #define CONFIG_SYS_FLASH_CFI 1
198 #define CONFIG_FLASH_CFI_DRIVER 1
199 #define PHYS_FLASH_1 0x10000000
200 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
201 #define CONFIG_SYS_MAX_FLASH_SECT 256
202 #define CONFIG_SYS_MAX_FLASH_BANKS 1
205 #ifdef CONFIG_CMD_NAND
206 #define CONFIG_NAND_ATMEL
207 #define CONFIG_SYS_NAND_MAX_CHIPS 1
208 #define CONFIG_SYS_MAX_NAND_DEVICE 1
209 #define CONFIG_SYS_NAND_BASE 0x40000000
210 #define CONFIG_SYS_NAND_DBW_8 1
211 /* our ALE is AD21 */
212 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
213 /* our CLE is AD22 */
214 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
215 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
216 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PB30
219 #define CONFIG_CMD_JFFS2 1
220 #define CONFIG_JFFS2_CMDLINE 1
221 #define CONFIG_JFFS2_NAND 1
222 #define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */
223 #define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */
224 #define CONFIG_JFFS2_PART_SIZE (256 * 1024 * 1024) /* partition size*/
227 #define PHYS_PSRAM 0x70000000
228 #define PHYS_PSRAM_SIZE 0x00400000 /* 4MB */
231 #define CONFIG_MACB 1
232 #define CONFIG_RMII 1
233 #define CONFIG_NET_MULTI 1
234 #define CONFIG_NET_RETRY_COUNT 20
235 #define CONFIG_RESET_PHY_R 1
238 #define CONFIG_USB_ATMEL
239 #define CONFIG_USB_OHCI_NEW 1
240 #define CONFIG_DOS_PARTITION 1
241 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1
242 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */
243 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263"
244 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
245 #define CONFIG_USB_STORAGE 1
247 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
249 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
250 #define CONFIG_SYS_MEMTEST_END 0x23e00000
252 #define CONFIG_SYS_USE_FLASH 1
253 #undef CONFIG_SYS_USE_DATAFLASH
254 #undef CONFIG_SYS_USE_NANDFLASH
256 #ifdef CONFIG_SYS_USE_DATAFLASH
258 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
259 #define CONFIG_ENV_IS_IN_DATAFLASH
260 #define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
261 #define CONFIG_ENV_OFFSET 0x4200
262 #define CONFIG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
263 #define CONFIG_ENV_SIZE 0x4200
264 #define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm"
265 #define CONFIG_BOOTARGS "console=ttyS0,115200 " \
266 "root=/dev/mtdblock0 " \
267 "mtdparts=at91_nand:-(root) "\
268 "rw rootfstype=jffs2"
270 #elif defined(CONFIG_SYS_USE_NANDFLASH) /* CFG_USE_NANDFLASH */
272 /* bootstrap + u-boot + env + linux in nandflash */
273 #define CONFIG_ENV_IS_IN_NAND
274 #define CONFIG_ENV_OFFSET 0x60000
275 #define CONFIG_ENV_OFFSET_REDUND 0x80000
276 #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
277 #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm"
278 #define CONFIG_BOOTARGS "console=ttyS0,115200 " \
279 "root=/dev/mtdblock5 " \
280 "mtdparts=at91_nand:" \
281 "128k(bootstrap)ro," \
287 "rw rootfstype=jffs2"
289 #elif defined(CONFIG_SYS_USE_FLASH) /* CFG_USE_FLASH */
291 #define CONFIG_ENV_IS_IN_FLASH 1
292 #define CONFIG_ENV_OFFSET 0x40000
293 #define CONFIG_ENV_SECT_SIZE 0x10000
294 #define CONFIG_ENV_SIZE 0x10000
295 #define CONFIG_ENV_OVERWRITE 1
297 /* JFFS Partition offset set */
298 #define CONFIG_SYS_JFFS2_FIRST_BANK 0
299 #define CONFIG_SYS_JFFS2_NUM_BANKS 1
301 /* 512k reserved for u-boot */
302 #define CONFIG_SYS_JFFS2_FIRST_SECTOR 11
304 #define CONFIG_BOOTCOMMAND "run flashboot"
305 #define CONFIG_ROOTPATH /ronetix/rootfs
306 #define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n"
308 #define CONFIG_CON_ROT "fbcon=rotate:3 "
309 #define CONFIG_BOOTARGS "root=/dev/mtdblock4 rootfstype=jffs2 "\
312 #define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=nand"
313 #define MTDPARTS_DEFAULT \
314 "mtdparts=physmap-flash.0:" \
316 "64k(u-boot-env)ro," \
321 #define CONFIG_EXTRA_ENV_SETTINGS \
322 "mtdids=" MTDIDS_DEFAULT "\0" \
323 "mtdparts=" MTDPARTS_DEFAULT "\0" \
324 "partition=nand0,0\0" \
325 "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
326 "nfsargs=setenv bootargs root=/dev/nfs rw " \
328 "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \
329 "addip=setenv bootargs $(bootargs) " \
330 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
331 ":$(hostname):eth0:off\0" \
332 "ramboot=tftpboot 0x22000000 vmImage;" \
333 "run ramargs;run addip;bootm 22000000\0" \
334 "nfsboot=tftpboot 0x22000000 vmImage;" \
335 "run nfsargs;run addip;bootm 22000000\0" \
336 "flashboot=run ramargs;run addip;bootm 0x10050000\0" \
340 #error "Undefined memory device"
343 #define CONFIG_BAUDRATE 115200
344 #define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
346 #define CONFIG_SYS_PROMPT "u-boot-pm9263> "
347 #define CONFIG_SYS_CBSIZE 256
348 #define CONFIG_SYS_MAXARGS 16
349 #define CONFIG_SYS_PBSIZE \
350 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
351 #define CONFIG_SYS_LONGHELP 1
352 #define CONFIG_CMDLINE_EDITING 1
354 #define ROUND(A, B) (((A) + (B)) & ~((B) - 1))
356 * Size of malloc() pool
358 #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
359 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
361 #define CONFIG_STACKSIZE (32 * 1024) /* regular stack */
363 #ifdef CONFIG_USE_IRQ
364 #error CONFIG_USE_IRQ not supported