1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2007-2008
4 * Stelian Pop <stelian@popies.net>
5 * Lead Tech Design <www.leadtechdesign.com>
6 * Ilko Iliev <www.ronetix.at>
8 * Configuration settings for the RONETIX PM9263 board.
15 * SoC must be defined first, before hardware.h is included.
16 * In this case SoC is defined in boards.cfg.
18 #include <asm/hardware.h>
20 /* ARM asynchronous clock */
22 #define MASTER_PLL_DIV 6
23 #define MASTER_PLL_MUL 65
24 #define MAIN_PLL_DIV 2 /* 2 or 4 */
25 #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000
26 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
28 #define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9263"
31 #define CONFIG_SYS_MOR_VAL \
32 (AT91_PMC_MOR_MOSCEN | \
33 (255 << 8)) /* Main Oscillator Start-up Time */
34 #define CONFIG_SYS_PLLAR_VAL \
35 (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \
36 AT91_PMC_PLLXR_OUT(3) | \
37 AT91_PMC_PLLXR_PLLCOUNT(0x3f) | /* PLL Counter */\
38 (2 << 28) | /* PLL Clock Frequency Range */ \
39 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
41 #if (MAIN_PLL_DIV == 2)
42 /* PCK/2 = MCK Master Clock from PLLA */
43 #define CONFIG_SYS_MCKR1_VAL \
44 (AT91_PMC_MCKR_CSS_SLOW | \
45 AT91_PMC_MCKR_PRES_1 | \
47 /* PCK/2 = MCK Master Clock from PLLA */
48 #define CONFIG_SYS_MCKR2_VAL \
49 (AT91_PMC_MCKR_CSS_PLLA | \
50 AT91_PMC_MCKR_PRES_1 | \
53 /* PCK/4 = MCK Master Clock from PLLA */
54 #define CONFIG_SYS_MCKR1_VAL \
55 (AT91_PMC_MCKR_CSS_SLOW | \
56 AT91_PMC_MCKR_PRES_1 | \
58 /* PCK/4 = MCK Master Clock from PLLA */
59 #define CONFIG_SYS_MCKR2_VAL \
60 (AT91_PMC_MCKR_CSS_PLLA | \
61 AT91_PMC_MCKR_PRES_1 | \
64 /* define PDC[31:16] as DATA[31:16] */
65 #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
66 /* no pull-up for D[31:16] */
67 #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
68 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
69 #define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
70 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \
71 AT91_MATRIX_CSA_EBI_CS1A)
74 /* SDRAMC_MR Mode register */
75 #define CONFIG_SYS_SDRC_MR_VAL1 0
76 /* SDRAMC_TR - Refresh Timer register */
77 #define CONFIG_SYS_SDRC_TR_VAL1 0x3AA
78 /* SDRAMC_CR - Configuration register*/
79 #define CONFIG_SYS_SDRC_CR_VAL \
84 AT91_SDRAMC_DBW_32 | \
85 (2 << 8) | /* tWR - Write Recovery Delay */ \
86 (7 << 12) | /* tRC - Row Cycle Delay */ \
87 (2 << 16) | /* tRP - Row Precharge Delay */ \
88 (2 << 20) | /* tRCD - Row to Column Delay */ \
89 (5 << 24) | /* tRAS - Active to Precharge Delay */ \
90 (8 << 28)) /* tXSR - Exit Self Refresh to Active Delay */
92 /* Memory Device Register -> SDRAM */
93 #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
94 #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
95 #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
96 #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
97 #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
98 #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
99 #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
100 #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
101 #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
102 #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
103 #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
104 #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
105 #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
106 #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
107 #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
108 #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
109 #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
110 #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
112 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
113 #define CONFIG_SYS_SMC0_SETUP0_VAL \
114 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \
115 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
116 #define CONFIG_SYS_SMC0_PULSE0_VAL \
117 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \
118 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
119 #define CONFIG_SYS_SMC0_CYCLE0_VAL \
120 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
121 #define CONFIG_SYS_SMC0_MODE0_VAL \
122 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
123 AT91_SMC_MODE_DBW_16 | \
124 AT91_SMC_MODE_TDF | \
125 AT91_SMC_MODE_TDF_CYCLE(6))
127 /* user reset enable */
128 #define CONFIG_SYS_RSTC_RMR_VAL \
130 AT91_RSTC_CR_PROCRST | \
131 AT91_RSTC_MR_ERSTL(1) | \
132 AT91_RSTC_MR_ERSTL(2))
134 /* Disable Watchdog */
135 #define CONFIG_SYS_WDTC_WDMR_VAL \
136 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
137 AT91_WDT_MR_WDV(0xfff) | \
138 AT91_WDT_MR_WDDIS | \
139 AT91_WDT_MR_WDD(0xfff))
141 #define CONFIG_USER_LOWLEVEL_INIT 1
147 #define LCD_BPP LCD_COLOR8
148 #define CONFIG_LCD_LOGO 1
149 #undef LCD_TEST_PATTERN
150 #define CONFIG_LCD_INFO 1
151 #define CONFIG_LCD_INFO_BELOW_LOGO 1
152 #define CONFIG_ATMEL_LCD 1
153 #define CONFIG_ATMEL_LCD_BGR555 1
155 #define CONFIG_LCD_IN_PSRAM 1
160 #define CONFIG_BOOTP_BOOTFILESIZE 1
163 #define PHYS_SDRAM 0x20000000
164 #define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
166 /* NOR flash, if populated */
167 #define PHYS_FLASH_1 0x10000000
168 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
169 #define CONFIG_SYS_MAX_FLASH_SECT 256
170 #define CONFIG_SYS_MAX_FLASH_BANKS 1
173 #ifdef CONFIG_CMD_NAND
174 #define CONFIG_SYS_MAX_NAND_DEVICE 1
175 #define CONFIG_SYS_NAND_BASE 0x40000000
176 #define CONFIG_SYS_NAND_DBW_8 1
177 /* our ALE is AD21 */
178 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
179 /* our CLE is AD22 */
180 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
181 #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15)
182 #define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PB(30)
186 #define CONFIG_JFFS2_NAND 1
187 #define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */
188 #define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */
189 #define CONFIG_JFFS2_PART_SIZE (256 * 1024 * 1024) /* partition size*/
192 #define PHYS_PSRAM 0x70000000
193 #define PHYS_PSRAM_SIZE 0x00400000 /* 4MB */
194 /* Slave EBI1, PSRAM connected */
195 #define CONFIG_PSRAM_SCFG (AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY | \
196 AT91_MATRIX_SCFG_FIXED_DEFMSTR(5) | \
197 AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED | \
198 AT91_MATRIX_SCFG_SLOT_CYCLE(255))
201 #define CONFIG_USB_ATMEL
202 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
203 #define CONFIG_USB_OHCI_NEW 1
204 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1
205 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */
206 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263"
207 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
209 #define CONFIG_SYS_USE_FLASH 1
210 #undef CONFIG_SYS_USE_DATAFLASH
211 #undef CONFIG_SYS_USE_NANDFLASH
213 #ifdef CONFIG_SYS_USE_DATAFLASH
215 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
216 #define CONFIG_BOOTCOMMAND "sf probe 0; " \
217 "sf read 0x22000000 0x84000 0x294000; " \
220 #elif defined(CONFIG_SYS_USE_NANDFLASH) /* CFG_USE_NANDFLASH */
222 /* bootstrap + u-boot + env + linux in nandflash */
223 #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm"
225 #elif defined(CONFIG_SYS_USE_FLASH) /* CFG_USE_FLASH */
226 /* JFFS Partition offset set */
227 #define CONFIG_SYS_JFFS2_FIRST_BANK 0
228 #define CONFIG_SYS_JFFS2_NUM_BANKS 1
230 /* 512k reserved for u-boot */
231 #define CONFIG_SYS_JFFS2_FIRST_SECTOR 11
233 #define CONFIG_BOOTCOMMAND "run flashboot"
234 #define CONFIG_ROOTPATH "/ronetix/rootfs"
236 #define CONFIG_CON_ROT "fbcon=rotate:3 "
238 #define CONFIG_EXTRA_ENV_SETTINGS \
239 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
240 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
241 "partition=nand0,0\0" \
242 "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
243 "nfsargs=setenv bootargs root=/dev/nfs rw " \
245 "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \
246 "addip=setenv bootargs $(bootargs) " \
247 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
248 ":$(hostname):eth0:off\0" \
249 "ramboot=tftpboot 0x22000000 vmImage;" \
250 "run ramargs;run addip;bootm 22000000\0" \
251 "nfsboot=tftpboot 0x22000000 vmImage;" \
252 "run nfsargs;run addip;bootm 22000000\0" \
253 "flashboot=run ramargs;run addip;bootm 0x10050000\0" \
257 #error "Undefined memory device"
260 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
261 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - \
262 GENERATED_GBL_DATA_SIZE)