Merge branch 'master' of git://git.denx.de/u-boot-imx
[platform/kernel/u-boot.git] / include / configs / pm9261.h
1 /*
2  * (C) Copyright 2007-2008
3  * Stelian Pop <stelian.pop@leadtechdesign.com>
4  * Lead Tech Design <www.leadtechdesign.com>
5  * Ilko Iliev <www.ronetix.at>
6  *
7  * Configuation settings for the RONETIX PM9261 board.
8  *
9  * See file CREDITS for list of people who contributed to this
10  * project.
11  *
12  * This program is free software; you can redistribute it and/or
13  * modify it under the terms of the GNU General Public License as
14  * published by the Free Software Foundation; either version 2 of
15  * the License, or (at your option) any later version.
16  *
17  * This program is distributed in the hope that it will be useful,
18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20  * GNU General Public License for more details.
21  *
22  * You should have received a copy of the GNU General Public License
23  * along with this program; if not, write to the Free Software
24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25  * MA 02111-1307 USA
26  */
27
28 #ifndef __CONFIG_H
29 #define __CONFIG_H
30
31 /* ARM asynchronous clock */
32 #define CONFIG_SYS_AT91_CPU_NAME        "AT91SAM9261"
33
34 #define CONFIG_DISPLAY_BOARDINFO
35
36 #define MASTER_PLL_DIV          15
37 #define MASTER_PLL_MUL          162
38 #define MAIN_PLL_DIV            2
39 #define CONFIG_SYS_AT91_MAIN_CLOCK      18432000
40
41 #define CONFIG_SYS_HZ           1000
42
43 #define CONFIG_ARM926EJS        1       /* This is an ARM926EJS Core    */
44 #define CONFIG_AT91SAM9261      1       /* It's an Atmel AT91SAM9261 SoC*/
45 #define CONFIG_PM9261           1       /* on a Ronetix PM9261 Board    */
46 #define CONFIG_ARCH_CPU_INIT
47 #undef CONFIG_USE_IRQ                   /* we don't need IRQ/FIQ stuff  */
48
49 /* clocks */
50 /* CKGR_MOR - enable main osc. */
51 #define CONFIG_SYS_MOR_VAL                                              \
52                 (AT91_PMC_MOR_MOSCEN |                                  \
53                  (255 << 8))            /* Main Oscillator Start-up Time */
54 #define CONFIG_SYS_PLLAR_VAL                                            \
55                 (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \
56                  AT91_PMC_PLLXR_OUT(3) |                                                \
57                  ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
58
59 /* PCK/2 = MCK Master Clock from PLLA */
60 #define CONFIG_SYS_MCKR1_VAL            \
61                 (AT91_PMC_MCKR_CSS_SLOW |       \
62                  AT91_PMC_MCKR_PRES_1 | \
63                  AT91_PMC_MCKR_MDIV_2 | \
64                  AT91_PMC_MCKR_PLLADIV_1)
65
66 /* PCK/2 = MCK Master Clock from PLLA */
67 #define CONFIG_SYS_MCKR2_VAL            \
68                 (AT91_PMC_MCKR_CSS_PLLA |       \
69                  AT91_PMC_MCKR_PRES_1 | \
70                  AT91_PMC_MCKR_MDIV_2 | \
71                  AT91_PMC_MCKR_PLLADIV_1)
72
73 /* define PDC[31:16] as DATA[31:16] */
74 #define CONFIG_SYS_PIOC_PDR_VAL1        0xFFFF0000
75 /* no pull-up for D[31:16] */
76 #define CONFIG_SYS_PIOC_PPUDR_VAL       0xFFFF0000
77
78 /* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
79 #define CONFIG_SYS_MATRIX_EBICSA_VAL            \
80         (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A)
81
82 /* SDRAM */
83 /* SDRAMC_MR Mode register */
84 #define CONFIG_SYS_SDRC_MR_VAL1         AT91_SDRAMC_MODE_NORMAL
85 /* SDRAMC_TR - Refresh Timer register */
86 #define CONFIG_SYS_SDRC_TR_VAL1         0x13C
87 /* SDRAMC_CR - Configuration register*/
88 #define CONFIG_SYS_SDRC_CR_VAL                                                  \
89                 (AT91_SDRAMC_NC_9 |                                             \
90                  AT91_SDRAMC_NR_13 |                                            \
91                  AT91_SDRAMC_NB_4 |                                             \
92                  AT91_SDRAMC_CAS_3 |                                            \
93                  AT91_SDRAMC_DBW_32 |                                           \
94                  (1 <<  8) |            /* Write Recovery Delay */              \
95                  (7 << 12) |            /* Row Cycle Delay */                   \
96                  (3 << 16) |            /* Row Precharge Delay */               \
97                  (2 << 20) |            /* Row to Column Delay */               \
98                  (5 << 24) |            /* Active to Precharge Delay */         \
99                  (1 << 28))             /* Exit Self Refresh to Active Delay */
100
101 /* Memory Device Register -> SDRAM */
102 #define CONFIG_SYS_SDRC_MDR_VAL         AT91_SDRAMC_MD_SDRAM
103 #define CONFIG_SYS_SDRC_MR_VAL2         AT91_SDRAMC_MODE_PRECHARGE
104 #define CONFIG_SYS_SDRAM_VAL1           0               /* SDRAM_BASE */
105 #define CONFIG_SYS_SDRC_MR_VAL3         AT91_SDRAMC_MODE_REFRESH
106 #define CONFIG_SYS_SDRAM_VAL2           0               /* SDRAM_BASE */
107 #define CONFIG_SYS_SDRAM_VAL3           0               /* SDRAM_BASE */
108 #define CONFIG_SYS_SDRAM_VAL4           0               /* SDRAM_BASE */
109 #define CONFIG_SYS_SDRAM_VAL5           0               /* SDRAM_BASE */
110 #define CONFIG_SYS_SDRAM_VAL6           0               /* SDRAM_BASE */
111 #define CONFIG_SYS_SDRAM_VAL7           0               /* SDRAM_BASE */
112 #define CONFIG_SYS_SDRAM_VAL8           0               /* SDRAM_BASE */
113 #define CONFIG_SYS_SDRAM_VAL9           0               /* SDRAM_BASE */
114 #define CONFIG_SYS_SDRC_MR_VAL4         AT91_SDRAMC_MODE_LMR
115 #define CONFIG_SYS_SDRAM_VAL10          0               /* SDRAM_BASE */
116 #define CONFIG_SYS_SDRC_MR_VAL5         AT91_SDRAMC_MODE_NORMAL
117 #define CONFIG_SYS_SDRAM_VAL11          0               /* SDRAM_BASE */
118 #define CONFIG_SYS_SDRC_TR_VAL2         1200            /* SDRAM_TR */
119 #define CONFIG_SYS_SDRAM_VAL12          0               /* SDRAM_BASE */
120
121 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
122 #define CONFIG_SYS_SMC0_SETUP0_VAL                                      \
123                 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) |   \
124                  AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
125 #define CONFIG_SYS_SMC0_PULSE0_VAL                                      \
126                 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) |   \
127                  AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
128 #define CONFIG_SYS_SMC0_CYCLE0_VAL      \
129                 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
130 #define CONFIG_SYS_SMC0_MODE0_VAL                               \
131                 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |  \
132                  AT91_SMC_MODE_DBW_16 |                         \
133                  AT91_SMC_MODE_TDF |                            \
134                  AT91_SMC_MODE_TDF_CYCLE(6))
135
136 /* user reset enable */
137 #define CONFIG_SYS_RSTC_RMR_VAL                 \
138                 (AT91_RSTC_KEY |                \
139                 AT91_RSTC_CR_PROCRST |          \
140                 AT91_RSTC_MR_ERSTL(1) | \
141                 AT91_RSTC_MR_ERSTL(2))
142
143 /* Disable Watchdog */
144 #define CONFIG_SYS_WDTC_WDMR_VAL                                \
145                 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
146                  AT91_WDT_MR_WDV(0xfff) |                                       \
147                  AT91_WDT_MR_WDDIS |                            \
148                  AT91_WDT_MR_WDD(0xfff))
149
150 #define CONFIG_CMDLINE_TAG      1       /* enable passing of ATAGs */
151 #define CONFIG_SETUP_MEMORY_TAGS 1
152 #define CONFIG_INITRD_TAG       1
153
154 #undef CONFIG_SKIP_LOWLEVEL_INIT
155
156 /*
157  * Hardware drivers
158  */
159 #define CONFIG_AT91_GPIO        1
160 #define CONFIG_ATMEL_USART      1
161 #undef CONFIG_USART0
162 #undef CONFIG_USART1
163 #undef CONFIG_USART2
164 #define CONFIG_USART3           1       /* USART 3 is DBGU */
165
166 /* LCD */
167 #define CONFIG_LCD                      1
168 #define LCD_BPP                         LCD_COLOR8
169 #define CONFIG_LCD_LOGO                 1
170 #undef LCD_TEST_PATTERN
171 #define CONFIG_LCD_INFO                 1
172 #define CONFIG_LCD_INFO_BELOW_LOGO      1
173 #define CONFIG_SYS_WHITE_ON_BLACK       1
174 #define CONFIG_ATMEL_LCD                1
175 #define CONFIG_ATMEL_LCD_BGR555         1
176 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    1
177
178 /* LED */
179 #define CONFIG_AT91_LED
180 #define CONFIG_RED_LED          AT91_PIO_PORTC, 12
181 #define CONFIG_GREEN_LED        AT91_PIO_PORTC, 13
182 #define CONFIG_YELLOW_LED       AT91_PIO_PORTC, 15
183
184 #define CONFIG_BOOTDELAY        3
185
186 /*
187  * BOOTP options
188  */
189 #define CONFIG_BOOTP_BOOTFILESIZE       1
190 #define CONFIG_BOOTP_BOOTPATH           1
191 #define CONFIG_BOOTP_GATEWAY            1
192 #define CONFIG_BOOTP_HOSTNAME           1
193
194 /*
195  * Command line configuration.
196  */
197 #include <config_cmd_default.h>
198 #undef CONFIG_CMD_BDI
199 #undef CONFIG_CMD_IMI
200 #undef CONFIG_CMD_FPGA
201 #undef CONFIG_CMD_LOADS
202 #undef CONFIG_CMD_IMLS
203
204 #define CONFIG_CMD_PING         1
205 #define CONFIG_CMD_DHCP         1
206 #define CONFIG_CMD_NAND         1
207 #define CONFIG_CMD_USB          1
208
209 /* SDRAM */
210 #define CONFIG_NR_DRAM_BANKS                    1
211 #define PHYS_SDRAM                              0x20000000
212 #define PHYS_SDRAM_SIZE                         0x04000000      /* 64 megs */
213
214 /* DataFlash */
215 #define CONFIG_ATMEL_DATAFLASH_SPI
216 #define CONFIG_HAS_DATAFLASH
217 #define CONFIG_SYS_SPI_WRITE_TOUT               (5 * CONFIG_SYS_HZ)
218 #define CONFIG_SYS_MAX_DATAFLASH_BANKS          1
219 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0     0xC0000000      /* CS0 */
220 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3     0xD0000000      /* CS3 */
221 #define AT91_SPI_CLK                            15000000
222 #define DATAFLASH_TCSS                          (0x1a << 16)
223 #define DATAFLASH_TCHS                          (0x1 << 24)
224
225 /* NAND flash */
226 #define CONFIG_NAND_ATMEL
227 #define NAND_MAX_CHIPS                          1
228 #define CONFIG_SYS_MAX_NAND_DEVICE              1
229 #define CONFIG_SYS_NAND_BASE                    0x40000000
230 #define CONFIG_SYS_NAND_DBW_8                   1
231 /* our ALE is AD22 */
232 #define CONFIG_SYS_NAND_MASK_ALE                (1 << 22)
233 /* our CLE is AD21 */
234 #define CONFIG_SYS_NAND_MASK_CLE                (1 << 21)
235 #define CONFIG_SYS_NAND_ENABLE_PIN              AT91_PIO_PORTC, 14
236 #define CONFIG_SYS_NAND_READY_PIN               AT91_PIO_PORTA, 16
237
238 /* NOR flash */
239 #define CONFIG_SYS_FLASH_CFI                    1
240 #define CONFIG_FLASH_CFI_DRIVER                 1
241 #define PHYS_FLASH_1                            0x10000000
242 #define CONFIG_SYS_FLASH_BASE                   PHYS_FLASH_1
243 #define CONFIG_SYS_MAX_FLASH_SECT               256
244 #define CONFIG_SYS_MAX_FLASH_BANKS              1
245
246 /* Ethernet */
247 #define CONFIG_DRIVER_DM9000                    1
248 #define CONFIG_DM9000_BASE                      0x30000000
249 #define DM9000_IO                               CONFIG_DM9000_BASE
250 #define DM9000_DATA                             (CONFIG_DM9000_BASE + 4)
251 #define CONFIG_DM9000_USE_16BIT                 1
252 #define CONFIG_NET_RETRY_COUNT                  20
253 #define CONFIG_RESET_PHY_R                      1
254 #define CONFIG_NET_MULTI
255
256 /* USB */
257 #define CONFIG_USB_ATMEL
258 #define CONFIG_USB_OHCI_NEW                     1
259 #define CONFIG_DOS_PARTITION                    1
260 #define CONFIG_SYS_USB_OHCI_CPU_INIT            1
261 #define CONFIG_SYS_USB_OHCI_REGS_BASE           0x00500000
262 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "at91sam9261"
263 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      2
264 #define CONFIG_USB_STORAGE                      1
265
266 #define CONFIG_SYS_LOAD_ADDR                    0x22000000
267
268 #define CONFIG_SYS_MEMTEST_START                PHYS_SDRAM
269 #define CONFIG_SYS_MEMTEST_END                  0x23e00000
270
271 #undef CONFIG_SYS_USE_DATAFLASH_CS0
272 #undef CONFIG_SYS_USE_NANDFLASH
273 #define CONFIG_SYS_USE_FLASH    1
274
275 #ifdef CONFIG_SYS_USE_DATAFLASH_CS0
276
277 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
278 #define CONFIG_ENV_IS_IN_DATAFLASH      1
279 #define CONFIG_SYS_MONITOR_BASE         \
280                 (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
281 #define CONFIG_ENV_OFFSET       0x4200
282 #define CONFIG_ENV_ADDR         \
283                 (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
284 #define CONFIG_ENV_SIZE         0x4200
285 #define CONFIG_BOOTCOMMAND      "cp.b 0xC0042000 0x22000000 0x210000; bootm"
286 #define CONFIG_BOOTARGS         "console=ttyS0,115200 "                 \
287                                 "root=/dev/mtdblock0 "                  \
288                                 "mtdparts=atmel_nand:-(root) "          \
289                                 "rw rootfstype=jffs2"
290
291 #elif defined(CONFIG_SYS_USE_NANDFLASH) /* CONFIG_SYS_USE_NANDFLASH */
292
293 /* bootstrap + u-boot + env + linux in nandflash */
294 #define CONFIG_ENV_IS_IN_NAND           1
295 #define CONFIG_ENV_OFFSET               0x60000
296 #define CONFIG_ENV_OFFSET_REDUND        0x80000
297 #define CONFIG_ENV_SIZE                 0x20000         /* 1 sector = 128 kB */
298 #define CONFIG_BOOTCOMMAND      "nand read 0x22000000 0xA0000 0x200000; bootm"
299 #define CONFIG_BOOTARGS         "console=ttyS0,115200 "                 \
300                                 "root=/dev/mtdblock5 "                  \
301                                 "mtdparts=atmel_nand:128k(bootstrap)ro,"        \
302                                 "256k(uboot)ro,128k(env1)ro,"           \
303                                 "128k(env2)ro,2M(linux),-(root) "       \
304                                 "rw rootfstype=jffs2"
305
306 #elif defined (CONFIG_SYS_USE_FLASH)
307
308 #define CONFIG_ENV_IS_IN_FLASH  1
309 #define CONFIG_ENV_OFFSET       0x40000
310 #define CONFIG_ENV_SECT_SIZE    0x10000
311 #define CONFIG_ENV_SIZE         0x10000
312 #define CONFIG_ENV_OVERWRITE    1
313
314 /* JFFS Partition offset set */
315 #define CONFIG_SYS_JFFS2_FIRST_BANK     0
316 #define CONFIG_SYS_JFFS2_NUM_BANKS      1
317
318 /* 512k reserved for u-boot */
319 #define CONFIG_SYS_JFFS2_FIRST_SECTOR   11
320
321 #define CONFIG_BOOTCOMMAND      "run flashboot"
322
323 #define MTDIDS_DEFAULT          "nor0=physmap-flash.0,nand0=nand"
324 #define MTDPARTS_DEFAULT                \
325         "mtdparts=physmap-flash.0:"     \
326                 "256k(u-boot)ro,"       \
327                 "64k(u-boot-env)ro,"    \
328                 "1408k(kernel),"        \
329                 "-(rootfs);"            \
330         "nand:-(nand)"
331
332 #define CONFIG_CON_ROT "fbcon=rotate:3 "
333 #define CONFIG_BOOTARGS "root=/dev/mtdblock4 rootfstype=jffs2 " CONFIG_CON_ROT
334
335 #define CONFIG_EXTRA_ENV_SETTINGS                               \
336         "mtdids=" MTDIDS_DEFAULT "\0"                           \
337         "mtdparts=" MTDPARTS_DEFAULT "\0"                       \
338         "partition=nand0,0\0"                                   \
339         "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0"     \
340         "nfsargs=setenv bootargs root=/dev/nfs rw "             \
341                 CONFIG_CON_ROT                                  \
342                 "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \
343         "addip=setenv bootargs $(bootargs) "                    \
344                 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
345                 ":$(hostname):eth0:off\0"                       \
346         "ramboot=tftpboot 0x22000000 vmImage;"                  \
347                 "run ramargs;run addip;bootm 22000000\0"        \
348         "nfsboot=tftpboot 0x22000000 vmImage;"                  \
349                 "run nfsargs;run addip;bootm 22000000\0"        \
350         "flashboot=run ramargs;run addip;bootm 0x10050000\0"    \
351         ""
352 #else
353 #error "Undefined memory device"
354 #endif
355
356 #define CONFIG_BAUDRATE                 115200
357 #define CONFIG_SYS_BAUDRATE_TABLE       {115200 , 19200, 38400, 57600, 9600 }
358
359 #define CONFIG_SYS_PROMPT               "pm9261> "
360 #define CONFIG_SYS_CBSIZE               256
361 #define CONFIG_SYS_MAXARGS              16
362 #define CONFIG_SYS_PBSIZE               \
363                 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
364 #define CONFIG_SYS_LONGHELP             1
365 #define CONFIG_CMDLINE_EDITING  1
366
367 /*
368  * Size of malloc() pool
369  */
370 #define CONFIG_SYS_MALLOC_LEN           \
371                 ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
372
373 #define CONFIG_STACKSIZE                (32 * 1024)     /* regular stack */
374
375 #ifdef CONFIG_USE_IRQ
376 #error CONFIG_USE_IRQ not supported
377 #endif
378
379 #endif