include/configs/pm9261.h

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian@popies.net>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  * Ilko Iliev <www.ronetix.at>
   6  *
   7  * Configuation settings for the RONETIX PM9261 board.
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * SoC must be defined first, before hardware.h is included.
  17  * In this case SoC is defined in boards.cfg.
  18  */
  19
  20 #include <asm/hardware.h>
  21 /* ARM asynchronous clock */
  22
  23 #define MASTER_PLL_DIV          15
  24 #define MASTER_PLL_MUL          162
  25 #define MAIN_PLL_DIV            2
  26 #define CONFIG_SYS_AT91_SLOW_CLOCK      32768           /* slow clock xtal */
  27 #define CONFIG_SYS_AT91_MAIN_CLOCK      18432000
  28
  29 #define CONFIG_SYS_AT91_CPU_NAME        "AT91SAM9261"
  30 #define CONFIG_ARCH_CPU_INIT
  31
  32 #define CONFIG_MACH_TYPE        MACH_TYPE_PM9261
  33
  34 /* clocks */
  35 /* CKGR_MOR - enable main osc. */
  36 #define CONFIG_SYS_MOR_VAL                                              \
  37                 (AT91_PMC_MOR_MOSCEN |                                  \
  38                  (255 << 8))            /* Main Oscillator Start-up Time */
  39 #define CONFIG_SYS_PLLAR_VAL                                            \
  40                 (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \
  41                  AT91_PMC_PLLXR_OUT(3) |                                                \
  42                  ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
  43
  44 /* PCK/2 = MCK Master Clock from PLLA */
  45 #define CONFIG_SYS_MCKR1_VAL            \
  46                 (AT91_PMC_MCKR_CSS_SLOW |       \
  47                  AT91_PMC_MCKR_PRES_1 | \
  48                  AT91_PMC_MCKR_MDIV_2)
  49
  50 /* PCK/2 = MCK Master Clock from PLLA */
  51 #define CONFIG_SYS_MCKR2_VAL            \
  52                 (AT91_PMC_MCKR_CSS_PLLA |       \
  53                  AT91_PMC_MCKR_PRES_1 | \
  54                  AT91_PMC_MCKR_MDIV_2)
  55
  56 /* define PDC[31:16] as DATA[31:16] */
  57 #define CONFIG_SYS_PIOC_PDR_VAL1        0xFFFF0000
  58 /* no pull-up for D[31:16] */
  59 #define CONFIG_SYS_PIOC_PPUDR_VAL       0xFFFF0000
  60
  61 /* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
  62 #define CONFIG_SYS_MATRIX_EBICSA_VAL            \
  63         (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A)
  64
  65 /* SDRAM */
  66 /* SDRAMC_MR Mode register */
  67 #define CONFIG_SYS_SDRC_MR_VAL1         AT91_SDRAMC_MODE_NORMAL
  68 /* SDRAMC_TR - Refresh Timer register */
  69 #define CONFIG_SYS_SDRC_TR_VAL1         0x13C
  70 /* SDRAMC_CR - Configuration register*/
  71 #define CONFIG_SYS_SDRC_CR_VAL                                                  \
  72                 (AT91_SDRAMC_NC_9 |                                             \
  73                  AT91_SDRAMC_NR_13 |                                            \
  74                  AT91_SDRAMC_NB_4 |                                             \
  75                  AT91_SDRAMC_CAS_3 |                                            \
  76                  AT91_SDRAMC_DBW_32 |                                           \
  77                  (1 <<  8) |            /* Write Recovery Delay */              \
  78                  (7 << 12) |            /* Row Cycle Delay */                   \
  79                  (3 << 16) |            /* Row Precharge Delay */               \
  80                  (2 << 20) |            /* Row to Column Delay */               \
  81                  (5 << 24) |            /* Active to Precharge Delay */         \
  82                  (1 << 28))             /* Exit Self Refresh to Active Delay */
  83
  84 /* Memory Device Register -> SDRAM */
  85 #define CONFIG_SYS_SDRC_MDR_VAL         AT91_SDRAMC_MD_SDRAM
  86 #define CONFIG_SYS_SDRC_MR_VAL2         AT91_SDRAMC_MODE_PRECHARGE
  87 #define CONFIG_SYS_SDRAM_VAL1           0               /* SDRAM_BASE */
  88 #define CONFIG_SYS_SDRC_MR_VAL3         AT91_SDRAMC_MODE_REFRESH
  89 #define CONFIG_SYS_SDRAM_VAL2           0               /* SDRAM_BASE */
  90 #define CONFIG_SYS_SDRAM_VAL3           0               /* SDRAM_BASE */
  91 #define CONFIG_SYS_SDRAM_VAL4           0               /* SDRAM_BASE */
  92 #define CONFIG_SYS_SDRAM_VAL5           0               /* SDRAM_BASE */
  93 #define CONFIG_SYS_SDRAM_VAL6           0               /* SDRAM_BASE */
  94 #define CONFIG_SYS_SDRAM_VAL7           0               /* SDRAM_BASE */
  95 #define CONFIG_SYS_SDRAM_VAL8           0               /* SDRAM_BASE */
  96 #define CONFIG_SYS_SDRAM_VAL9           0               /* SDRAM_BASE */
  97 #define CONFIG_SYS_SDRC_MR_VAL4         AT91_SDRAMC_MODE_LMR
  98 #define CONFIG_SYS_SDRAM_VAL10          0               /* SDRAM_BASE */
  99 #define CONFIG_SYS_SDRC_MR_VAL5         AT91_SDRAMC_MODE_NORMAL
 100 #define CONFIG_SYS_SDRAM_VAL11          0               /* SDRAM_BASE */
 101 #define CONFIG_SYS_SDRC_TR_VAL2         1200            /* SDRAM_TR */
 102 #define CONFIG_SYS_SDRAM_VAL12          0               /* SDRAM_BASE */
 103
 104 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
 105 #define CONFIG_SYS_SMC0_SETUP0_VAL                                      \
 106                 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) |   \
 107                  AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
 108 #define CONFIG_SYS_SMC0_PULSE0_VAL                                      \
 109                 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) |   \
 110                  AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
 111 #define CONFIG_SYS_SMC0_CYCLE0_VAL      \
 112                 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
 113 #define CONFIG_SYS_SMC0_MODE0_VAL                               \
 114                 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |  \
 115                  AT91_SMC_MODE_DBW_16 |                         \
 116                  AT91_SMC_MODE_TDF |                            \
 117                  AT91_SMC_MODE_TDF_CYCLE(6))
 118
 119 /* user reset enable */
 120 #define CONFIG_SYS_RSTC_RMR_VAL                 \
 121                 (AT91_RSTC_KEY |                \
 122                 AT91_RSTC_CR_PROCRST |          \
 123                 AT91_RSTC_MR_ERSTL(1) | \
 124                 AT91_RSTC_MR_ERSTL(2))
 125
 126 /* Disable Watchdog */
 127 #define CONFIG_SYS_WDTC_WDMR_VAL                                \
 128                 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
 129                  AT91_WDT_MR_WDV(0xfff) |                                       \
 130                  AT91_WDT_MR_WDDIS |                            \
 131                  AT91_WDT_MR_WDD(0xfff))
 132
 133 #define CONFIG_CMDLINE_TAG      1       /* enable passing of ATAGs */
 134 #define CONFIG_SETUP_MEMORY_TAGS 1
 135 #define CONFIG_INITRD_TAG       1
 136
 137 #undef CONFIG_SKIP_LOWLEVEL_INIT
 138
 139 /*
 140  * Hardware drivers
 141  */
 142
 143 /* LCD */
 144 #define LCD_BPP                         LCD_COLOR8
 145 #define CONFIG_LCD_LOGO                 1
 146 #undef LCD_TEST_PATTERN
 147 #define CONFIG_LCD_INFO                 1
 148 #define CONFIG_LCD_INFO_BELOW_LOGO      1
 149 #define CONFIG_ATMEL_LCD                1
 150 #define CONFIG_ATMEL_LCD_BGR555         1
 151
 152 /*
 153  * BOOTP options
 154  */
 155 #define CONFIG_BOOTP_BOOTFILESIZE       1
 156
 157 /* SDRAM */
 158 #define CONFIG_NR_DRAM_BANKS                    1
 159 #define PHYS_SDRAM                              0x20000000
 160 #define PHYS_SDRAM_SIZE                         0x04000000      /* 64 megs */
 161
 162 /* NAND flash */
 163 #define CONFIG_NAND_ATMEL
 164 #define CONFIG_SYS_MAX_NAND_DEVICE              1
 165 #define CONFIG_SYS_NAND_BASE                    0x40000000
 166 #define CONFIG_SYS_NAND_DBW_8                   1
 167 /* our ALE is AD22 */
 168 #define CONFIG_SYS_NAND_MASK_ALE                (1 << 22)
 169 /* our CLE is AD21 */
 170 #define CONFIG_SYS_NAND_MASK_CLE                (1 << 21)
 171 #define CONFIG_SYS_NAND_ENABLE_PIN              GPIO_PIN_PC(14)
 172 #define CONFIG_SYS_NAND_READY_PIN               GPIO_PIN_PA(16)
 173
 174 /* NOR flash */
 175 #define CONFIG_SYS_FLASH_CFI                    1
 176 #define CONFIG_FLASH_CFI_DRIVER                 1
 177 #define PHYS_FLASH_1                            0x10000000
 178 #define CONFIG_SYS_FLASH_BASE                   PHYS_FLASH_1
 179 #define CONFIG_SYS_MAX_FLASH_SECT               256
 180 #define CONFIG_SYS_MAX_FLASH_BANKS              1
 181
 182 /* Ethernet */
 183 #define CONFIG_DRIVER_DM9000                    1
 184 #define CONFIG_DM9000_BASE                      0x30000000
 185 #define DM9000_IO                               CONFIG_DM9000_BASE
 186 #define DM9000_DATA                             (CONFIG_DM9000_BASE + 4)
 187 #define CONFIG_DM9000_USE_16BIT                 1
 188 #define CONFIG_NET_RETRY_COUNT                  20
 189 #define CONFIG_RESET_PHY_R                      1
 190
 191 /* USB */
 192 #define CONFIG_USB_ATMEL
 193 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
 194 #define CONFIG_USB_OHCI_NEW                     1
 195 #define CONFIG_SYS_USB_OHCI_CPU_INIT            1
 196 #define CONFIG_SYS_USB_OHCI_REGS_BASE           0x00500000
 197 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "at91sam9261"
 198 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      2
 199
 200 #define CONFIG_SYS_LOAD_ADDR                    0x22000000
 201
 202 #define CONFIG_SYS_MEMTEST_START                PHYS_SDRAM
 203 #define CONFIG_SYS_MEMTEST_END                  0x23e00000
 204
 205 #undef CONFIG_SYS_USE_DATAFLASH_CS0
 206 #undef CONFIG_SYS_USE_NANDFLASH
 207 #define CONFIG_SYS_USE_FLASH    1
 208
 209 #ifdef CONFIG_SYS_USE_DATAFLASH_CS0
 210
 211 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
 212 #define CONFIG_ENV_OFFSET       0x4200
 213 #define CONFIG_ENV_SIZE         0x4200
 214 #define CONFIG_ENV_SECT_SIZE    0x210
 215 #define CONFIG_ENV_SPI_MAX_HZ   15000000
 216 #define CONFIG_BOOTCOMMAND      "sf probe 0; " \
 217                                 "sf read 0x22000000 0x84000 0x210000; " \
 218                                 "bootm 0x22000000"
 219
 220 #elif defined(CONFIG_SYS_USE_NANDFLASH) /* CONFIG_SYS_USE_NANDFLASH */
 221
 222 /* bootstrap + u-boot + env + linux in nandflash */
 223 #define CONFIG_ENV_OFFSET               0x60000
 224 #define CONFIG_ENV_OFFSET_REDUND        0x80000
 225 #define CONFIG_ENV_SIZE                 0x20000         /* 1 sector = 128 kB */
 226 #define CONFIG_BOOTCOMMAND      "nand read 0x22000000 0xA0000 0x200000; bootm"
 227
 228 #elif defined (CONFIG_SYS_USE_FLASH)
 229
 230 #define CONFIG_ENV_OFFSET       0x40000
 231 #define CONFIG_ENV_SECT_SIZE    0x10000
 232 #define CONFIG_ENV_SIZE         0x10000
 233 #define CONFIG_ENV_OVERWRITE    1
 234
 235 /* JFFS Partition offset set */
 236 #define CONFIG_SYS_JFFS2_FIRST_BANK     0
 237 #define CONFIG_SYS_JFFS2_NUM_BANKS      1
 238
 239 /* 512k reserved for u-boot */
 240 #define CONFIG_SYS_JFFS2_FIRST_SECTOR   11
 241
 242 #define CONFIG_BOOTCOMMAND      "run flashboot"
 243
 244 #define CONFIG_CON_ROT "fbcon=rotate:3 "
 245
 246 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 247         "mtdids=" CONFIG_MTDIDS_DEFAULT "\0"                            \
 248         "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"                        \
 249         "partition=nand0,0\0"                                   \
 250         "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0"     \
 251         "nfsargs=setenv bootargs root=/dev/nfs rw "             \
 252                 CONFIG_CON_ROT                                  \
 253                 "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \
 254         "addip=setenv bootargs $(bootargs) "                    \
 255                 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
 256                 ":$(hostname):eth0:off\0"                       \
 257         "ramboot=tftpboot 0x22000000 vmImage;"                  \
 258                 "run ramargs;run addip;bootm 22000000\0"        \
 259         "nfsboot=tftpboot 0x22000000 vmImage;"                  \
 260                 "run nfsargs;run addip;bootm 22000000\0"        \
 261         "flashboot=run ramargs;run addip;bootm 0x10050000\0"    \
 262         ""
 263 #else
 264 #error "Undefined memory device"
 265 #endif
 266
 267 /*
 268  * Size of malloc() pool
 269  */
 270 #define CONFIG_SYS_MALLOC_LEN           \
 271                 ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
 272
 273 #define CONFIG_SYS_SDRAM_BASE   PHYS_SDRAM
 274 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - \
 275                                 GENERATED_GBL_DATA_SIZE)
 276
 277 #endif