include/configs/pm9261.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2007-2008
   4  * Stelian Pop <stelian@popies.net>
   5  * Lead Tech Design <www.leadtechdesign.com>
   6  * Ilko Iliev <www.ronetix.at>
   7  *
   8  * Configuation settings for the RONETIX PM9261 board.
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 /*
  15  * SoC must be defined first, before hardware.h is included.
  16  * In this case SoC is defined in boards.cfg.
  17  */
  18
  19 #include <asm/hardware.h>
  20 /* ARM asynchronous clock */
  21
  22 #define MASTER_PLL_DIV          15
  23 #define MASTER_PLL_MUL          162
  24 #define MAIN_PLL_DIV            2
  25 #define CONFIG_SYS_AT91_SLOW_CLOCK      32768           /* slow clock xtal */
  26 #define CONFIG_SYS_AT91_MAIN_CLOCK      18432000
  27
  28 #define CONFIG_SYS_AT91_CPU_NAME        "AT91SAM9261"
  29 #define CONFIG_ARCH_CPU_INIT
  30
  31 #define CONFIG_MACH_TYPE        MACH_TYPE_PM9261
  32
  33 /* clocks */
  34 /* CKGR_MOR - enable main osc. */
  35 #define CONFIG_SYS_MOR_VAL                                              \
  36                 (AT91_PMC_MOR_MOSCEN |                                  \
  37                  (255 << 8))            /* Main Oscillator Start-up Time */
  38 #define CONFIG_SYS_PLLAR_VAL                                            \
  39                 (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \
  40                  AT91_PMC_PLLXR_OUT(3) |                                                \
  41                  ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
  42
  43 /* PCK/2 = MCK Master Clock from PLLA */
  44 #define CONFIG_SYS_MCKR1_VAL            \
  45                 (AT91_PMC_MCKR_CSS_SLOW |       \
  46                  AT91_PMC_MCKR_PRES_1 | \
  47                  AT91_PMC_MCKR_MDIV_2)
  48
  49 /* PCK/2 = MCK Master Clock from PLLA */
  50 #define CONFIG_SYS_MCKR2_VAL            \
  51                 (AT91_PMC_MCKR_CSS_PLLA |       \
  52                  AT91_PMC_MCKR_PRES_1 | \
  53                  AT91_PMC_MCKR_MDIV_2)
  54
  55 /* define PDC[31:16] as DATA[31:16] */
  56 #define CONFIG_SYS_PIOC_PDR_VAL1        0xFFFF0000
  57 /* no pull-up for D[31:16] */
  58 #define CONFIG_SYS_PIOC_PPUDR_VAL       0xFFFF0000
  59
  60 /* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
  61 #define CONFIG_SYS_MATRIX_EBICSA_VAL            \
  62         (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A)
  63
  64 /* SDRAM */
  65 /* SDRAMC_MR Mode register */
  66 #define CONFIG_SYS_SDRC_MR_VAL1         AT91_SDRAMC_MODE_NORMAL
  67 /* SDRAMC_TR - Refresh Timer register */
  68 #define CONFIG_SYS_SDRC_TR_VAL1         0x13C
  69 /* SDRAMC_CR - Configuration register*/
  70 #define CONFIG_SYS_SDRC_CR_VAL                                                  \
  71                 (AT91_SDRAMC_NC_9 |                                             \
  72                  AT91_SDRAMC_NR_13 |                                            \
  73                  AT91_SDRAMC_NB_4 |                                             \
  74                  AT91_SDRAMC_CAS_3 |                                            \
  75                  AT91_SDRAMC_DBW_32 |                                           \
  76                  (1 <<  8) |            /* Write Recovery Delay */              \
  77                  (7 << 12) |            /* Row Cycle Delay */                   \
  78                  (3 << 16) |            /* Row Precharge Delay */               \
  79                  (2 << 20) |            /* Row to Column Delay */               \
  80                  (5 << 24) |            /* Active to Precharge Delay */         \
  81                  (1 << 28))             /* Exit Self Refresh to Active Delay */
  82
  83 /* Memory Device Register -> SDRAM */
  84 #define CONFIG_SYS_SDRC_MDR_VAL         AT91_SDRAMC_MD_SDRAM
  85 #define CONFIG_SYS_SDRC_MR_VAL2         AT91_SDRAMC_MODE_PRECHARGE
  86 #define CONFIG_SYS_SDRAM_VAL1           0               /* SDRAM_BASE */
  87 #define CONFIG_SYS_SDRC_MR_VAL3         AT91_SDRAMC_MODE_REFRESH
  88 #define CONFIG_SYS_SDRAM_VAL2           0               /* SDRAM_BASE */
  89 #define CONFIG_SYS_SDRAM_VAL3           0               /* SDRAM_BASE */
  90 #define CONFIG_SYS_SDRAM_VAL4           0               /* SDRAM_BASE */
  91 #define CONFIG_SYS_SDRAM_VAL5           0               /* SDRAM_BASE */
  92 #define CONFIG_SYS_SDRAM_VAL6           0               /* SDRAM_BASE */
  93 #define CONFIG_SYS_SDRAM_VAL7           0               /* SDRAM_BASE */
  94 #define CONFIG_SYS_SDRAM_VAL8           0               /* SDRAM_BASE */
  95 #define CONFIG_SYS_SDRAM_VAL9           0               /* SDRAM_BASE */
  96 #define CONFIG_SYS_SDRC_MR_VAL4         AT91_SDRAMC_MODE_LMR
  97 #define CONFIG_SYS_SDRAM_VAL10          0               /* SDRAM_BASE */
  98 #define CONFIG_SYS_SDRC_MR_VAL5         AT91_SDRAMC_MODE_NORMAL
  99 #define CONFIG_SYS_SDRAM_VAL11          0               /* SDRAM_BASE */
 100 #define CONFIG_SYS_SDRC_TR_VAL2         1200            /* SDRAM_TR */
 101 #define CONFIG_SYS_SDRAM_VAL12          0               /* SDRAM_BASE */
 102
 103 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
 104 #define CONFIG_SYS_SMC0_SETUP0_VAL                                      \
 105                 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) |   \
 106                  AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
 107 #define CONFIG_SYS_SMC0_PULSE0_VAL                                      \
 108                 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) |   \
 109                  AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
 110 #define CONFIG_SYS_SMC0_CYCLE0_VAL      \
 111                 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
 112 #define CONFIG_SYS_SMC0_MODE0_VAL                               \
 113                 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |  \
 114                  AT91_SMC_MODE_DBW_16 |                         \
 115                  AT91_SMC_MODE_TDF |                            \
 116                  AT91_SMC_MODE_TDF_CYCLE(6))
 117
 118 /* user reset enable */
 119 #define CONFIG_SYS_RSTC_RMR_VAL                 \
 120                 (AT91_RSTC_KEY |                \
 121                 AT91_RSTC_CR_PROCRST |          \
 122                 AT91_RSTC_MR_ERSTL(1) | \
 123                 AT91_RSTC_MR_ERSTL(2))
 124
 125 /* Disable Watchdog */
 126 #define CONFIG_SYS_WDTC_WDMR_VAL                                \
 127                 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
 128                  AT91_WDT_MR_WDV(0xfff) |                                       \
 129                  AT91_WDT_MR_WDDIS |                            \
 130                  AT91_WDT_MR_WDD(0xfff))
 131
 132 #define CONFIG_CMDLINE_TAG      1       /* enable passing of ATAGs */
 133 #define CONFIG_SETUP_MEMORY_TAGS 1
 134 #define CONFIG_INITRD_TAG       1
 135
 136 #undef CONFIG_SKIP_LOWLEVEL_INIT
 137
 138 /*
 139  * Hardware drivers
 140  */
 141
 142 /* LCD */
 143 #define LCD_BPP                         LCD_COLOR8
 144 #define CONFIG_LCD_LOGO                 1
 145 #undef LCD_TEST_PATTERN
 146 #define CONFIG_LCD_INFO                 1
 147 #define CONFIG_LCD_INFO_BELOW_LOGO      1
 148 #define CONFIG_ATMEL_LCD                1
 149 #define CONFIG_ATMEL_LCD_BGR555         1
 150
 151 /*
 152  * BOOTP options
 153  */
 154 #define CONFIG_BOOTP_BOOTFILESIZE       1
 155
 156 /* SDRAM */
 157 #define PHYS_SDRAM                              0x20000000
 158 #define PHYS_SDRAM_SIZE                         0x04000000      /* 64 megs */
 159
 160 /* NAND flash */
 161 #define CONFIG_SYS_MAX_NAND_DEVICE              1
 162 #define CONFIG_SYS_NAND_BASE                    0x40000000
 163 #define CONFIG_SYS_NAND_DBW_8                   1
 164 /* our ALE is AD22 */
 165 #define CONFIG_SYS_NAND_MASK_ALE                (1 << 22)
 166 /* our CLE is AD21 */
 167 #define CONFIG_SYS_NAND_MASK_CLE                (1 << 21)
 168 #define CONFIG_SYS_NAND_ENABLE_PIN              GPIO_PIN_PC(14)
 169 #define CONFIG_SYS_NAND_READY_PIN               GPIO_PIN_PA(16)
 170
 171 /* NOR flash */
 172 #define PHYS_FLASH_1                            0x10000000
 173 #define CONFIG_SYS_FLASH_BASE                   PHYS_FLASH_1
 174 #define CONFIG_SYS_MAX_FLASH_SECT               256
 175 #define CONFIG_SYS_MAX_FLASH_BANKS              1
 176
 177 /* Ethernet */
 178 #define CONFIG_DRIVER_DM9000                    1
 179 #define CONFIG_DM9000_BASE                      0x30000000
 180 #define DM9000_IO                               CONFIG_DM9000_BASE
 181 #define DM9000_DATA                             (CONFIG_DM9000_BASE + 4)
 182 #define CONFIG_DM9000_USE_16BIT                 1
 183 #define CONFIG_NET_RETRY_COUNT                  20
 184 #define CONFIG_RESET_PHY_R                      1
 185
 186 /* USB */
 187 #define CONFIG_USB_ATMEL
 188 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
 189 #define CONFIG_USB_OHCI_NEW                     1
 190 #define CONFIG_SYS_USB_OHCI_CPU_INIT            1
 191 #define CONFIG_SYS_USB_OHCI_REGS_BASE           0x00500000
 192 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "at91sam9261"
 193 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      2
 194
 195 #define CONFIG_SYS_LOAD_ADDR                    0x22000000
 196
 197 #define CONFIG_SYS_MEMTEST_START                PHYS_SDRAM
 198 #define CONFIG_SYS_MEMTEST_END                  0x23e00000
 199
 200 #undef CONFIG_SYS_USE_DATAFLASH_CS0
 201 #undef CONFIG_SYS_USE_NANDFLASH
 202 #define CONFIG_SYS_USE_FLASH    1
 203
 204 #ifdef CONFIG_SYS_USE_DATAFLASH_CS0
 205
 206 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
 207 #define CONFIG_ENV_OFFSET       0x4200
 208 #define CONFIG_ENV_SIZE         0x4200
 209 #define CONFIG_ENV_SECT_SIZE    0x210
 210 #define CONFIG_BOOTCOMMAND      "sf probe 0; " \
 211                                 "sf read 0x22000000 0x84000 0x210000; " \
 212                                 "bootm 0x22000000"
 213
 214 #elif defined(CONFIG_SYS_USE_NANDFLASH) /* CONFIG_SYS_USE_NANDFLASH */
 215
 216 /* bootstrap + u-boot + env + linux in nandflash */
 217 #define CONFIG_ENV_OFFSET               0x60000
 218 #define CONFIG_ENV_OFFSET_REDUND        0x80000
 219 #define CONFIG_ENV_SIZE                 0x20000         /* 1 sector = 128 kB */
 220 #define CONFIG_BOOTCOMMAND      "nand read 0x22000000 0xA0000 0x200000; bootm"
 221
 222 #elif defined (CONFIG_SYS_USE_FLASH)
 223
 224 #define CONFIG_ENV_OFFSET       0x40000
 225 #define CONFIG_ENV_SECT_SIZE    0x10000
 226 #define CONFIG_ENV_SIZE         0x10000
 227 #define CONFIG_ENV_OVERWRITE    1
 228
 229 /* JFFS Partition offset set */
 230 #define CONFIG_SYS_JFFS2_FIRST_BANK     0
 231 #define CONFIG_SYS_JFFS2_NUM_BANKS      1
 232
 233 /* 512k reserved for u-boot */
 234 #define CONFIG_SYS_JFFS2_FIRST_SECTOR   11
 235
 236 #define CONFIG_BOOTCOMMAND      "run flashboot"
 237
 238 #define CONFIG_CON_ROT "fbcon=rotate:3 "
 239
 240 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 241         "mtdids=" CONFIG_MTDIDS_DEFAULT "\0"                            \
 242         "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"                        \
 243         "partition=nand0,0\0"                                   \
 244         "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0"     \
 245         "nfsargs=setenv bootargs root=/dev/nfs rw "             \
 246                 CONFIG_CON_ROT                                  \
 247                 "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \
 248         "addip=setenv bootargs $(bootargs) "                    \
 249                 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
 250                 ":$(hostname):eth0:off\0"                       \
 251         "ramboot=tftpboot 0x22000000 vmImage;"                  \
 252                 "run ramargs;run addip;bootm 22000000\0"        \
 253         "nfsboot=tftpboot 0x22000000 vmImage;"                  \
 254                 "run nfsargs;run addip;bootm 22000000\0"        \
 255         "flashboot=run ramargs;run addip;bootm 0x10050000\0"    \
 256         ""
 257 #else
 258 #error "Undefined memory device"
 259 #endif
 260
 261 /*
 262  * Size of malloc() pool
 263  */
 264 #define CONFIG_SYS_MALLOC_LEN           \
 265                 ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
 266
 267 #define CONFIG_SYS_SDRAM_BASE   PHYS_SDRAM
 268 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - \
 269                                 GENERATED_GBL_DATA_SIZE)
 270
 271 #endif