537a6d8ecf81c8b5da01dd49b19a355147b86d8d
[platform/kernel/u-boot.git] / include / configs / pm9261.h
1 /*
2  * (C) Copyright 2007-2008
3  * Stelian Pop <stelian@popies.net>
4  * Lead Tech Design <www.leadtechdesign.com>
5  * Ilko Iliev <www.ronetix.at>
6  *
7  * Configuation settings for the RONETIX PM9261 board.
8  *
9  * SPDX-License-Identifier:     GPL-2.0+
10  */
11
12 #ifndef __CONFIG_H
13 #define __CONFIG_H
14
15 /*
16  * SoC must be defined first, before hardware.h is included.
17  * In this case SoC is defined in boards.cfg.
18  */
19
20 #include <asm/hardware.h>
21 /* ARM asynchronous clock */
22
23 #define CONFIG_DISPLAY_BOARDINFO
24
25 #define MASTER_PLL_DIV          15
26 #define MASTER_PLL_MUL          162
27 #define MAIN_PLL_DIV            2
28 #define CONFIG_SYS_AT91_SLOW_CLOCK      32768           /* slow clock xtal */
29 #define CONFIG_SYS_AT91_MAIN_CLOCK      18432000
30
31 #define CONFIG_SYS_AT91_CPU_NAME        "AT91SAM9261"
32 #define CONFIG_PM9261           1       /* on a Ronetix PM9261 Board    */
33 #define CONFIG_ARCH_CPU_INIT
34 #define CONFIG_SYS_TEXT_BASE    0
35
36 #define MACH_TYPE_PM9261        1187
37 #define CONFIG_MACH_TYPE        MACH_TYPE_PM9261
38
39 /* clocks */
40 /* CKGR_MOR - enable main osc. */
41 #define CONFIG_SYS_MOR_VAL                                              \
42                 (AT91_PMC_MOR_MOSCEN |                                  \
43                  (255 << 8))            /* Main Oscillator Start-up Time */
44 #define CONFIG_SYS_PLLAR_VAL                                            \
45                 (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \
46                  AT91_PMC_PLLXR_OUT(3) |                                                \
47                  ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
48
49 /* PCK/2 = MCK Master Clock from PLLA */
50 #define CONFIG_SYS_MCKR1_VAL            \
51                 (AT91_PMC_MCKR_CSS_SLOW |       \
52                  AT91_PMC_MCKR_PRES_1 | \
53                  AT91_PMC_MCKR_MDIV_2)
54
55 /* PCK/2 = MCK Master Clock from PLLA */
56 #define CONFIG_SYS_MCKR2_VAL            \
57                 (AT91_PMC_MCKR_CSS_PLLA |       \
58                  AT91_PMC_MCKR_PRES_1 | \
59                  AT91_PMC_MCKR_MDIV_2)
60
61 /* define PDC[31:16] as DATA[31:16] */
62 #define CONFIG_SYS_PIOC_PDR_VAL1        0xFFFF0000
63 /* no pull-up for D[31:16] */
64 #define CONFIG_SYS_PIOC_PPUDR_VAL       0xFFFF0000
65
66 /* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
67 #define CONFIG_SYS_MATRIX_EBICSA_VAL            \
68         (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A)
69
70 /* SDRAM */
71 /* SDRAMC_MR Mode register */
72 #define CONFIG_SYS_SDRC_MR_VAL1         AT91_SDRAMC_MODE_NORMAL
73 /* SDRAMC_TR - Refresh Timer register */
74 #define CONFIG_SYS_SDRC_TR_VAL1         0x13C
75 /* SDRAMC_CR - Configuration register*/
76 #define CONFIG_SYS_SDRC_CR_VAL                                                  \
77                 (AT91_SDRAMC_NC_9 |                                             \
78                  AT91_SDRAMC_NR_13 |                                            \
79                  AT91_SDRAMC_NB_4 |                                             \
80                  AT91_SDRAMC_CAS_3 |                                            \
81                  AT91_SDRAMC_DBW_32 |                                           \
82                  (1 <<  8) |            /* Write Recovery Delay */              \
83                  (7 << 12) |            /* Row Cycle Delay */                   \
84                  (3 << 16) |            /* Row Precharge Delay */               \
85                  (2 << 20) |            /* Row to Column Delay */               \
86                  (5 << 24) |            /* Active to Precharge Delay */         \
87                  (1 << 28))             /* Exit Self Refresh to Active Delay */
88
89 /* Memory Device Register -> SDRAM */
90 #define CONFIG_SYS_SDRC_MDR_VAL         AT91_SDRAMC_MD_SDRAM
91 #define CONFIG_SYS_SDRC_MR_VAL2         AT91_SDRAMC_MODE_PRECHARGE
92 #define CONFIG_SYS_SDRAM_VAL1           0               /* SDRAM_BASE */
93 #define CONFIG_SYS_SDRC_MR_VAL3         AT91_SDRAMC_MODE_REFRESH
94 #define CONFIG_SYS_SDRAM_VAL2           0               /* SDRAM_BASE */
95 #define CONFIG_SYS_SDRAM_VAL3           0               /* SDRAM_BASE */
96 #define CONFIG_SYS_SDRAM_VAL4           0               /* SDRAM_BASE */
97 #define CONFIG_SYS_SDRAM_VAL5           0               /* SDRAM_BASE */
98 #define CONFIG_SYS_SDRAM_VAL6           0               /* SDRAM_BASE */
99 #define CONFIG_SYS_SDRAM_VAL7           0               /* SDRAM_BASE */
100 #define CONFIG_SYS_SDRAM_VAL8           0               /* SDRAM_BASE */
101 #define CONFIG_SYS_SDRAM_VAL9           0               /* SDRAM_BASE */
102 #define CONFIG_SYS_SDRC_MR_VAL4         AT91_SDRAMC_MODE_LMR
103 #define CONFIG_SYS_SDRAM_VAL10          0               /* SDRAM_BASE */
104 #define CONFIG_SYS_SDRC_MR_VAL5         AT91_SDRAMC_MODE_NORMAL
105 #define CONFIG_SYS_SDRAM_VAL11          0               /* SDRAM_BASE */
106 #define CONFIG_SYS_SDRC_TR_VAL2         1200            /* SDRAM_TR */
107 #define CONFIG_SYS_SDRAM_VAL12          0               /* SDRAM_BASE */
108
109 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
110 #define CONFIG_SYS_SMC0_SETUP0_VAL                                      \
111                 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) |   \
112                  AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
113 #define CONFIG_SYS_SMC0_PULSE0_VAL                                      \
114                 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) |   \
115                  AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
116 #define CONFIG_SYS_SMC0_CYCLE0_VAL      \
117                 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
118 #define CONFIG_SYS_SMC0_MODE0_VAL                               \
119                 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |  \
120                  AT91_SMC_MODE_DBW_16 |                         \
121                  AT91_SMC_MODE_TDF |                            \
122                  AT91_SMC_MODE_TDF_CYCLE(6))
123
124 /* user reset enable */
125 #define CONFIG_SYS_RSTC_RMR_VAL                 \
126                 (AT91_RSTC_KEY |                \
127                 AT91_RSTC_CR_PROCRST |          \
128                 AT91_RSTC_MR_ERSTL(1) | \
129                 AT91_RSTC_MR_ERSTL(2))
130
131 /* Disable Watchdog */
132 #define CONFIG_SYS_WDTC_WDMR_VAL                                \
133                 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
134                  AT91_WDT_MR_WDV(0xfff) |                                       \
135                  AT91_WDT_MR_WDDIS |                            \
136                  AT91_WDT_MR_WDD(0xfff))
137
138 #define CONFIG_CMDLINE_TAG      1       /* enable passing of ATAGs */
139 #define CONFIG_SETUP_MEMORY_TAGS 1
140 #define CONFIG_INITRD_TAG       1
141
142 #undef CONFIG_SKIP_LOWLEVEL_INIT
143 #define CONFIG_BOARD_EARLY_INIT_F
144
145 /*
146  * Hardware drivers
147  */
148 #define CONFIG_AT91_GPIO        1
149 #define CONFIG_ATMEL_USART      1
150 #define CONFIG_USART_BASE               ATMEL_BASE_DBGU
151 #define CONFIG_USART_ID                 ATMEL_ID_SYS
152
153 /* LCD */
154 #define CONFIG_LCD                      1
155 #define LCD_BPP                         LCD_COLOR8
156 #define CONFIG_LCD_LOGO                 1
157 #undef LCD_TEST_PATTERN
158 #define CONFIG_LCD_INFO                 1
159 #define CONFIG_LCD_INFO_BELOW_LOGO      1
160 #define CONFIG_SYS_WHITE_ON_BLACK       1
161 #define CONFIG_ATMEL_LCD                1
162 #define CONFIG_ATMEL_LCD_BGR555         1
163 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    1
164
165 /* LED */
166 #define CONFIG_AT91_LED
167 #define CONFIG_RED_LED          GPIO_PIN_PC(12)
168 #define CONFIG_GREEN_LED        GPIO_PIN_PC(13)
169 #define CONFIG_YELLOW_LED       GPIO_PIN_PC(15)
170
171
172 /*
173  * BOOTP options
174  */
175 #define CONFIG_BOOTP_BOOTFILESIZE       1
176 #define CONFIG_BOOTP_BOOTPATH           1
177 #define CONFIG_BOOTP_GATEWAY            1
178 #define CONFIG_BOOTP_HOSTNAME           1
179
180 /*
181  * Command line configuration.
182  */
183 #define CONFIG_CMD_NAND         1
184
185 /* SDRAM */
186 #define CONFIG_NR_DRAM_BANKS                    1
187 #define PHYS_SDRAM                              0x20000000
188 #define PHYS_SDRAM_SIZE                         0x04000000      /* 64 megs */
189
190 /* DataFlash */
191 #define CONFIG_ATMEL_DATAFLASH_SPI
192 #define CONFIG_HAS_DATAFLASH
193 #define CONFIG_SYS_MAX_DATAFLASH_BANKS          1
194 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0     0xC0000000      /* CS0 */
195 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3     0xD0000000      /* CS3 */
196 #define AT91_SPI_CLK                            15000000
197 #define DATAFLASH_TCSS                          (0x1a << 16)
198 #define DATAFLASH_TCHS                          (0x1 << 24)
199
200 /* NAND flash */
201 #define CONFIG_NAND_ATMEL
202 #define CONFIG_SYS_MAX_NAND_DEVICE              1
203 #define CONFIG_SYS_NAND_BASE                    0x40000000
204 #define CONFIG_SYS_NAND_DBW_8                   1
205 /* our ALE is AD22 */
206 #define CONFIG_SYS_NAND_MASK_ALE                (1 << 22)
207 /* our CLE is AD21 */
208 #define CONFIG_SYS_NAND_MASK_CLE                (1 << 21)
209 #define CONFIG_SYS_NAND_ENABLE_PIN              GPIO_PIN_PC(14)
210 #define CONFIG_SYS_NAND_READY_PIN               GPIO_PIN_PA(16)
211
212 /* NOR flash */
213 #define CONFIG_SYS_FLASH_CFI                    1
214 #define CONFIG_FLASH_CFI_DRIVER                 1
215 #define PHYS_FLASH_1                            0x10000000
216 #define CONFIG_SYS_FLASH_BASE                   PHYS_FLASH_1
217 #define CONFIG_SYS_MAX_FLASH_SECT               256
218 #define CONFIG_SYS_MAX_FLASH_BANKS              1
219
220 /* Ethernet */
221 #define CONFIG_DRIVER_DM9000                    1
222 #define CONFIG_DM9000_BASE                      0x30000000
223 #define DM9000_IO                               CONFIG_DM9000_BASE
224 #define DM9000_DATA                             (CONFIG_DM9000_BASE + 4)
225 #define CONFIG_DM9000_USE_16BIT                 1
226 #define CONFIG_NET_RETRY_COUNT                  20
227 #define CONFIG_RESET_PHY_R                      1
228
229 /* USB */
230 #define CONFIG_USB_ATMEL
231 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
232 #define CONFIG_USB_OHCI_NEW                     1
233 #define CONFIG_DOS_PARTITION                    1
234 #define CONFIG_SYS_USB_OHCI_CPU_INIT            1
235 #define CONFIG_SYS_USB_OHCI_REGS_BASE           0x00500000
236 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "at91sam9261"
237 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      2
238
239 #define CONFIG_SYS_LOAD_ADDR                    0x22000000
240
241 #define CONFIG_SYS_MEMTEST_START                PHYS_SDRAM
242 #define CONFIG_SYS_MEMTEST_END                  0x23e00000
243
244 #undef CONFIG_SYS_USE_DATAFLASH_CS0
245 #undef CONFIG_SYS_USE_NANDFLASH
246 #define CONFIG_SYS_USE_FLASH    1
247
248 #ifdef CONFIG_SYS_USE_DATAFLASH_CS0
249
250 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
251 #define CONFIG_ENV_IS_IN_DATAFLASH      1
252 #define CONFIG_SYS_MONITOR_BASE         \
253                 (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
254 #define CONFIG_ENV_OFFSET       0x4200
255 #define CONFIG_ENV_ADDR         \
256                 (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
257 #define CONFIG_ENV_SIZE         0x4200
258 #define CONFIG_BOOTCOMMAND      "cp.b 0xC0042000 0x22000000 0x210000; bootm"
259 #define CONFIG_BOOTARGS         "console=ttyS0,115200 "                 \
260                                 "root=/dev/mtdblock0 "                  \
261                                 "mtdparts=atmel_nand:-(root) "          \
262                                 "rw rootfstype=jffs2"
263
264 #elif defined(CONFIG_SYS_USE_NANDFLASH) /* CONFIG_SYS_USE_NANDFLASH */
265
266 /* bootstrap + u-boot + env + linux in nandflash */
267 #define CONFIG_ENV_IS_IN_NAND           1
268 #define CONFIG_ENV_OFFSET               0x60000
269 #define CONFIG_ENV_OFFSET_REDUND        0x80000
270 #define CONFIG_ENV_SIZE                 0x20000         /* 1 sector = 128 kB */
271 #define CONFIG_BOOTCOMMAND      "nand read 0x22000000 0xA0000 0x200000; bootm"
272 #define CONFIG_BOOTARGS         "console=ttyS0,115200 "                 \
273                                 "root=/dev/mtdblock5 "                  \
274                                 "mtdparts=atmel_nand:128k(bootstrap)ro,"        \
275                                 "256k(uboot)ro,128k(env1)ro,"           \
276                                 "128k(env2)ro,2M(linux),-(root) "       \
277                                 "rw rootfstype=jffs2"
278
279 #elif defined (CONFIG_SYS_USE_FLASH)
280
281 #define CONFIG_ENV_IS_IN_FLASH  1
282 #define CONFIG_ENV_OFFSET       0x40000
283 #define CONFIG_ENV_SECT_SIZE    0x10000
284 #define CONFIG_ENV_SIZE         0x10000
285 #define CONFIG_ENV_OVERWRITE    1
286
287 /* JFFS Partition offset set */
288 #define CONFIG_SYS_JFFS2_FIRST_BANK     0
289 #define CONFIG_SYS_JFFS2_NUM_BANKS      1
290
291 /* 512k reserved for u-boot */
292 #define CONFIG_SYS_JFFS2_FIRST_SECTOR   11
293
294 #define CONFIG_BOOTCOMMAND      "run flashboot"
295
296 #define MTDIDS_DEFAULT          "nor0=physmap-flash.0,nand0=nand"
297 #define MTDPARTS_DEFAULT                \
298         "mtdparts=physmap-flash.0:"     \
299                 "256k(u-boot)ro,"       \
300                 "64k(u-boot-env)ro,"    \
301                 "1408k(kernel),"        \
302                 "-(rootfs);"            \
303         "nand:-(nand)"
304
305 #define CONFIG_CON_ROT "fbcon=rotate:3 "
306 #define CONFIG_BOOTARGS "root=/dev/mtdblock4 rootfstype=jffs2 " CONFIG_CON_ROT
307
308 #define CONFIG_EXTRA_ENV_SETTINGS                               \
309         "mtdids=" MTDIDS_DEFAULT "\0"                           \
310         "mtdparts=" MTDPARTS_DEFAULT "\0"                       \
311         "partition=nand0,0\0"                                   \
312         "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0"     \
313         "nfsargs=setenv bootargs root=/dev/nfs rw "             \
314                 CONFIG_CON_ROT                                  \
315                 "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \
316         "addip=setenv bootargs $(bootargs) "                    \
317                 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
318                 ":$(hostname):eth0:off\0"                       \
319         "ramboot=tftpboot 0x22000000 vmImage;"                  \
320                 "run ramargs;run addip;bootm 22000000\0"        \
321         "nfsboot=tftpboot 0x22000000 vmImage;"                  \
322                 "run nfsargs;run addip;bootm 22000000\0"        \
323         "flashboot=run ramargs;run addip;bootm 0x10050000\0"    \
324         ""
325 #else
326 #error "Undefined memory device"
327 #endif
328
329 #define CONFIG_BAUDRATE                 115200
330
331 #define CONFIG_SYS_CBSIZE               256
332 #define CONFIG_SYS_MAXARGS              16
333 #define CONFIG_SYS_PBSIZE               \
334                 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
335 #define CONFIG_SYS_LONGHELP             1
336 #define CONFIG_CMDLINE_EDITING  1
337
338 /*
339  * Size of malloc() pool
340  */
341 #define CONFIG_SYS_MALLOC_LEN           \
342                 ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
343
344 #define CONFIG_SYS_SDRAM_BASE   PHYS_SDRAM
345 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
346                                 GENERATED_GBL_DATA_SIZE)
347
348 #endif