include/configs/pm9261.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2007-2008
   4  * Stelian Pop <stelian@popies.net>
   5  * Lead Tech Design <www.leadtechdesign.com>
   6  * Ilko Iliev <www.ronetix.at>
   7  *
   8  * Configuation settings for the RONETIX PM9261 board.
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 /*
  15  * SoC must be defined first, before hardware.h is included.
  16  * In this case SoC is defined in boards.cfg.
  17  */
  18
  19 #include <asm/hardware.h>
  20 /* ARM asynchronous clock */
  21
  22 #define MASTER_PLL_DIV          15
  23 #define MASTER_PLL_MUL          162
  24 #define MAIN_PLL_DIV            2
  25 #define CONFIG_SYS_AT91_SLOW_CLOCK      32768           /* slow clock xtal */
  26 #define CONFIG_SYS_AT91_MAIN_CLOCK      18432000
  27
  28 /* clocks */
  29 /* CKGR_MOR - enable main osc. */
  30 #define CONFIG_SYS_MOR_VAL                                              \
  31                 (AT91_PMC_MOR_MOSCEN |                                  \
  32                  (255 << 8))            /* Main Oscillator Start-up Time */
  33 #define CONFIG_SYS_PLLAR_VAL                                            \
  34                 (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \
  35                  AT91_PMC_PLLXR_OUT(3) |                                                \
  36                  ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
  37
  38 /* PCK/2 = MCK Master Clock from PLLA */
  39 #define CONFIG_SYS_MCKR1_VAL            \
  40                 (AT91_PMC_MCKR_CSS_SLOW |       \
  41                  AT91_PMC_MCKR_PRES_1 | \
  42                  AT91_PMC_MCKR_MDIV_2)
  43
  44 /* PCK/2 = MCK Master Clock from PLLA */
  45 #define CONFIG_SYS_MCKR2_VAL            \
  46                 (AT91_PMC_MCKR_CSS_PLLA |       \
  47                  AT91_PMC_MCKR_PRES_1 | \
  48                  AT91_PMC_MCKR_MDIV_2)
  49
  50 /* define PDC[31:16] as DATA[31:16] */
  51 #define CONFIG_SYS_PIOC_PDR_VAL1        0xFFFF0000
  52 /* no pull-up for D[31:16] */
  53 #define CONFIG_SYS_PIOC_PPUDR_VAL       0xFFFF0000
  54
  55 /* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
  56 #define CONFIG_SYS_MATRIX_EBICSA_VAL            \
  57         (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A)
  58
  59 /* SDRAM */
  60 /* SDRAMC_MR Mode register */
  61 #define CONFIG_SYS_SDRC_MR_VAL1         AT91_SDRAMC_MODE_NORMAL
  62 /* SDRAMC_TR - Refresh Timer register */
  63 #define CONFIG_SYS_SDRC_TR_VAL1         0x13C
  64 /* SDRAMC_CR - Configuration register*/
  65 #define CONFIG_SYS_SDRC_CR_VAL                                                  \
  66                 (AT91_SDRAMC_NC_9 |                                             \
  67                  AT91_SDRAMC_NR_13 |                                            \
  68                  AT91_SDRAMC_NB_4 |                                             \
  69                  AT91_SDRAMC_CAS_3 |                                            \
  70                  AT91_SDRAMC_DBW_32 |                                           \
  71                  (1 <<  8) |            /* Write Recovery Delay */              \
  72                  (7 << 12) |            /* Row Cycle Delay */                   \
  73                  (3 << 16) |            /* Row Precharge Delay */               \
  74                  (2 << 20) |            /* Row to Column Delay */               \
  75                  (5 << 24) |            /* Active to Precharge Delay */         \
  76                  (1 << 28))             /* Exit Self Refresh to Active Delay */
  77
  78 /* Memory Device Register -> SDRAM */
  79 #define CONFIG_SYS_SDRC_MDR_VAL         AT91_SDRAMC_MD_SDRAM
  80 #define CONFIG_SYS_SDRC_MR_VAL2         AT91_SDRAMC_MODE_PRECHARGE
  81 #define CONFIG_SYS_SDRAM_VAL1           0               /* SDRAM_BASE */
  82 #define CONFIG_SYS_SDRC_MR_VAL3         AT91_SDRAMC_MODE_REFRESH
  83 #define CONFIG_SYS_SDRAM_VAL2           0               /* SDRAM_BASE */
  84 #define CONFIG_SYS_SDRAM_VAL3           0               /* SDRAM_BASE */
  85 #define CONFIG_SYS_SDRAM_VAL4           0               /* SDRAM_BASE */
  86 #define CONFIG_SYS_SDRAM_VAL5           0               /* SDRAM_BASE */
  87 #define CONFIG_SYS_SDRAM_VAL6           0               /* SDRAM_BASE */
  88 #define CONFIG_SYS_SDRAM_VAL7           0               /* SDRAM_BASE */
  89 #define CONFIG_SYS_SDRAM_VAL8           0               /* SDRAM_BASE */
  90 #define CONFIG_SYS_SDRAM_VAL9           0               /* SDRAM_BASE */
  91 #define CONFIG_SYS_SDRC_MR_VAL4         AT91_SDRAMC_MODE_LMR
  92 #define CONFIG_SYS_SDRAM_VAL10          0               /* SDRAM_BASE */
  93 #define CONFIG_SYS_SDRC_MR_VAL5         AT91_SDRAMC_MODE_NORMAL
  94 #define CONFIG_SYS_SDRAM_VAL11          0               /* SDRAM_BASE */
  95 #define CONFIG_SYS_SDRC_TR_VAL2         1200            /* SDRAM_TR */
  96 #define CONFIG_SYS_SDRAM_VAL12          0               /* SDRAM_BASE */
  97
  98 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
  99 #define CONFIG_SYS_SMC0_SETUP0_VAL                                      \
 100                 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) |   \
 101                  AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
 102 #define CONFIG_SYS_SMC0_PULSE0_VAL                                      \
 103                 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) |   \
 104                  AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
 105 #define CONFIG_SYS_SMC0_CYCLE0_VAL      \
 106                 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
 107 #define CONFIG_SYS_SMC0_MODE0_VAL                               \
 108                 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |  \
 109                  AT91_SMC_MODE_DBW_16 |                         \
 110                  AT91_SMC_MODE_TDF |                            \
 111                  AT91_SMC_MODE_TDF_CYCLE(6))
 112
 113 /* user reset enable */
 114 #define CONFIG_SYS_RSTC_RMR_VAL                 \
 115                 (AT91_RSTC_KEY |                \
 116                 AT91_RSTC_CR_PROCRST |          \
 117                 AT91_RSTC_MR_ERSTL(1) | \
 118                 AT91_RSTC_MR_ERSTL(2))
 119
 120 /* Disable Watchdog */
 121 #define CONFIG_SYS_WDTC_WDMR_VAL                                \
 122                 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
 123                  AT91_WDT_MR_WDV(0xfff) |                                       \
 124                  AT91_WDT_MR_WDDIS |                            \
 125                  AT91_WDT_MR_WDD(0xfff))
 126
 127 /*
 128  * Hardware drivers
 129  */
 130
 131 /* LCD */
 132 #define LCD_BPP                         LCD_COLOR8
 133 #undef LCD_TEST_PATTERN
 134
 135 /* SDRAM */
 136 #define PHYS_SDRAM                              0x20000000
 137 #define PHYS_SDRAM_SIZE                         0x04000000      /* 64 megs */
 138
 139 /* NAND flash */
 140 #define CONFIG_SYS_MAX_NAND_DEVICE              1
 141 #define CONFIG_SYS_NAND_BASE                    0x40000000
 142 #define CONFIG_SYS_NAND_DBW_8                   1
 143 /* our ALE is AD22 */
 144 #define CONFIG_SYS_NAND_MASK_ALE                (1 << 22)
 145 /* our CLE is AD21 */
 146 #define CONFIG_SYS_NAND_MASK_CLE                (1 << 21)
 147 #define CONFIG_SYS_NAND_ENABLE_PIN              GPIO_PIN_PC(14)
 148 #define CONFIG_SYS_NAND_READY_PIN               GPIO_PIN_PA(16)
 149
 150 /* NOR flash */
 151 #define PHYS_FLASH_1                            0x10000000
 152 #define CONFIG_SYS_FLASH_BASE                   PHYS_FLASH_1
 153 #define CONFIG_SYS_MAX_FLASH_SECT               256
 154
 155 /* USB */
 156 #define CONFIG_USB_ATMEL
 157 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
 158 #define CONFIG_USB_OHCI_NEW                     1
 159 #define CONFIG_SYS_USB_OHCI_CPU_INIT            1
 160 #define CONFIG_SYS_USB_OHCI_REGS_BASE           0x00500000
 161 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "at91sam9261"
 162 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      2
 163
 164 #undef CONFIG_SYS_USE_DATAFLASH_CS0
 165 #undef CONFIG_SYS_USE_NANDFLASH
 166 #define CONFIG_SYS_USE_FLASH    1
 167
 168 #ifdef CONFIG_SYS_USE_DATAFLASH_CS0
 169
 170 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
 171
 172 #elif defined(CONFIG_SYS_USE_NANDFLASH) /* CONFIG_SYS_USE_NANDFLASH */
 173
 174 /* bootstrap + u-boot + env + linux in nandflash */
 175
 176 #elif defined (CONFIG_SYS_USE_FLASH)
 177 /* JFFS Partition offset set */
 178 #define CONFIG_SYS_JFFS2_FIRST_BANK     0
 179 #define CONFIG_SYS_JFFS2_NUM_BANKS      1
 180
 181 /* 512k reserved for u-boot */
 182 #define CONFIG_SYS_JFFS2_FIRST_SECTOR   11
 183
 184 #define CONFIG_CON_ROT "fbcon=rotate:3 "
 185
 186 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 187         "mtdids=" CONFIG_MTDIDS_DEFAULT "\0"                            \
 188         "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"                        \
 189         "partition=nand0,0\0"                                   \
 190         "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0"     \
 191         "nfsargs=setenv bootargs root=/dev/nfs rw "             \
 192                 CONFIG_CON_ROT                                  \
 193                 "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \
 194         "addip=setenv bootargs $(bootargs) "                    \
 195                 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
 196                 ":$(hostname):eth0:off\0"                       \
 197         "ramboot=tftpboot 0x22000000 vmImage;"                  \
 198                 "run ramargs;run addip;bootm 22000000\0"        \
 199         "nfsboot=tftpboot 0x22000000 vmImage;"                  \
 200                 "run nfsargs;run addip;bootm 22000000\0"        \
 201         "flashboot=run ramargs;run addip;bootm 0x10050000\0"    \
 202         ""
 203 #else
 204 #error "Undefined memory device"
 205 #endif
 206
 207 #define CONFIG_SYS_SDRAM_BASE   PHYS_SDRAM
 208 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - \
 209                                 GENERATED_GBL_DATA_SIZE)
 210
 211 #endif