1 /* SPDX-License-Identifier: GPL-2.0+ */
6 #ifndef __IMX8M_PICOPI_H
7 #define __IMX8M_PICOPI_H
9 #include <linux/sizes.h>
10 #include <asm/arch/imx-regs.h>
12 #define CONFIG_SPL_MAX_SIZE (124 * 1024)
13 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
14 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
15 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
16 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
18 #ifdef CONFIG_SPL_BUILD
19 /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
20 #define CONFIG_SPL_WATCHDOG_SUPPORT
21 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
22 #define CONFIG_SPL_POWER_SUPPORT
23 #define CONFIG_SPL_I2C_SUPPORT
24 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
25 #define CONFIG_SPL_STACK 0x187FF0
26 #define CONFIG_SPL_LIBCOMMON_SUPPORT
27 #define CONFIG_SPL_LIBGENERIC_SUPPORT
28 #define CONFIG_SPL_GPIO_SUPPORT
29 #define CONFIG_SPL_MMC_SUPPORT
30 #define CONFIG_SPL_BSS_START_ADDR 0x00180000
31 #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
32 #define CONFIG_SYS_SPL_MALLOC_START 0x42200000
33 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */
34 #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000
36 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
37 #define CONFIG_MALLOC_F_ADDR 0x182000
38 /* For RAW image gives a error info not panic */
39 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
44 #define CONFIG_SYS_I2C
45 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
46 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
47 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
49 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
52 #define CONFIG_POWER_I2C
55 #define CONFIG_REMAKE_ELF
57 #define CONFIG_BOARD_EARLY_INIT_F
58 #define CONFIG_BOARD_LATE_INIT
60 #undef CONFIG_CMD_EXPORTENV
61 #undef CONFIG_CMD_IMPORTENV
62 #undef CONFIG_CMD_IMLS
64 #undef CONFIG_CMD_CRC32
68 #if defined(CONFIG_CMD_NET)
69 #define CONFIG_CMD_PING
70 #define CONFIG_CMD_DHCP
71 #define CONFIG_CMD_MII
73 #define CONFIG_ETHPRIME "FEC"
75 #define CONFIG_FEC_MXC
76 #define CONFIG_FEC_XCV_TYPE RGMII
77 #define CONFIG_FEC_MXC_PHYADDR 1
78 #define FEC_QUIRK_ENET_MAC
80 #define CONFIG_PHY_GIGE
81 #define IMX_FEC_BASE 0x30BE0000
84 #define CONFIG_PHY_ATHEROS
87 /* Initial environment variables */
88 #define CONFIG_EXTRA_ENV_SETTINGS \
91 "console=ttymxc0,115200\0" \
92 "fdt_addr=0x43000000\0" \
93 "fdt_high=0xffffffffffffffff\0" \
94 "fdt_file=imx8mq-pico-pi.dtb\0" \
95 "initrd_addr=0x43800000\0" \
96 "initrd_high=0xffffffffffffffff\0" \
97 "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
98 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
99 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
100 "mmcautodetect=yes\0" \
101 "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
103 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
104 "bootscript=echo Running bootscript from mmc ...; source\0" \
105 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
106 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
107 "mmcboot=echo Booting from mmc ...; " \
109 "echo wait for boot; " \
111 "netargs=setenv bootargs console=${console} " \
113 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
114 "netboot=echo Booting from net ...; " \
116 "if test ${ip_dyn} = yes; then " \
117 "setenv get_cmd dhcp; " \
119 "setenv get_cmd tftp; " \
121 "${get_cmd} ${loadaddr} ${image}; " \
124 #define CONFIG_BOOTCOMMAND \
125 "mmc dev ${mmcdev}; if mmc rescan; then " \
126 "if run loadbootscript; then " \
129 "if run loadimage; then " \
131 "else run netboot; " \
134 "else booti ${loadaddr} - ${fdt_addr}; fi"
136 /* Link Definitions */
137 #define CONFIG_LOADADDR 0x40480000
139 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
141 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
142 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000
143 #define CONFIG_SYS_INIT_SP_OFFSET \
144 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
145 #define CONFIG_SYS_INIT_SP_ADDR \
146 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
148 #define CONFIG_ENV_OVERWRITE
149 #define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
150 #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
152 /* Size of malloc() pool */
153 #define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2 * 1024)) * 1024)
155 #define CONFIG_SYS_SDRAM_BASE 0x40000000
156 #define PHYS_SDRAM 0x40000000
157 #define PHYS_SDRAM_SIZE 0x80000000 /* 2 GiB DDR */
159 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
160 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
161 (PHYS_SDRAM_SIZE >> 1))
163 #define CONFIG_BAUDRATE 115200
165 #define CONFIG_MXC_UART
166 #define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
168 /* Monitor Command Prompt */
169 #define CONFIG_SYS_CBSIZE 1024
170 #define CONFIG_SYS_MAXARGS 64
171 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
172 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
173 sizeof(CONFIG_SYS_PROMPT) + 16)
175 #define CONFIG_IMX_BOOTAUX
177 #define CONFIG_SYS_FSL_USDHC_NUM 2
178 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
180 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1
182 #define CONFIG_MXC_GPIO
184 #define CONFIG_CMD_FUSE
187 #define CONFIG_SYS_I2C_SPEED 100000
189 #define CONFIG_OF_SYSTEM_SETUP
191 #ifndef CONFIG_SPL_BUILD
192 #define CONFIG_DM_PMIC
195 #define CONFIG_SYS_BOOTM_LEN SZ_128M