board: phytec: imx8mp: Add PHYTEC phyCORE-i.MX8MP support
[platform/kernel/u-boot.git] / include / configs / phycore_imx8mp.h
1 /* SPDX-License-Identifier: GPL-2.0-or-later
2  *
3  * Copyright (C) 2020 PHYTEC Messtechnik GmbH
4  * Author: Teresa Remmet <t.remmet@phytec.de>
5  */
6
7 #ifndef __PHYCORE_IMX8MP_H
8 #define __PHYCORE_IMX8MP_H
9
10 #include <linux/sizes.h>
11 #include <asm/arch/imx-regs.h>
12
13 #define CONFIG_SYS_BOOTM_LEN            SZ_64M
14
15 #define CONFIG_SPL_MAX_SIZE             (152 * SZ_1K)
16 #define CONFIG_SYS_MONITOR_LEN          SZ_512K
17 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
18 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
19 #define CONFIG_SYS_UBOOT_BASE \
20                 (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
21
22 #ifdef CONFIG_SPL_BUILD
23 #define CONFIG_SPL_LDSCRIPT             "arch/arm/cpu/armv8/u-boot-spl.lds"
24 #define CONFIG_SPL_STACK                0x960000
25 #define CONFIG_SPL_BSS_START_ADDR       0x98FC00
26 #define CONFIG_SPL_BSS_MAX_SIZE         SZ_1K
27 #define CONFIG_SYS_SPL_MALLOC_START     0x42200000
28 #define CONFIG_SYS_SPL_MALLOC_SIZE      SZ_512K
29
30 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
31
32 #define CONFIG_POWER
33 #define CONFIG_POWER_I2C
34 #define CONFIG_POWER_PCA9450
35
36 #undef CONFIG_DM_I2C
37 #define CONFIG_SYS_I2C
38
39 #endif
40
41 #define CONFIG_EXTRA_ENV_SETTINGS \
42         "image=Image\0" \
43         "console=ttymxc1,115200\0" \
44         "fdt_addr=0x48000000\0" \
45         "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
46         "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
47         "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
48         "mmcroot=2\0" \
49         "mmcautodetect=yes\0" \
50         "mmcargs=setenv bootargs console=${console} " \
51                 "root=/dev/mmcblk${mmcdev}p${mmcroot} rootwait rw\0" \
52         "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
53         "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
54         "mmcboot=echo Booting from mmc ...; " \
55                 "run mmcargs; " \
56                 "if run loadfdt; then " \
57                         "booti ${loadaddr} - ${fdt_addr}; " \
58                 "else " \
59                         "echo WARN: Cannot load the DT; " \
60                 "fi;\0 " \
61
62 #define CONFIG_BOOTCOMMAND \
63         "mmc dev ${mmcdev}; if mmc rescan; then " \
64                 "if run loadimage; then " \
65                         "run mmcboot; " \
66                 "else run netboot; " \
67                 "fi; " \
68         "fi;"
69
70 /* Link Definitions */
71 #define CONFIG_LOADADDR                 0x40480000
72 #define CONFIG_SYS_LOAD_ADDR            CONFIG_LOADADDR
73
74 #define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
75 #define CONFIG_SYS_INIT_RAM_SIZE        SZ_512K
76 #define CONFIG_SYS_INIT_SP_OFFSET \
77         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
78 #define CONFIG_SYS_INIT_SP_ADDR \
79         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
80
81 #define CONFIG_MMCROOT                  "/dev/mmcblk2p2"  /* USDHC3 */
82
83 /* Size of malloc() pool */
84 #define CONFIG_SYS_MALLOC_LEN           SZ_32M
85 #define CONFIG_SYS_SDRAM_BASE           0x40000000
86
87 #define PHYS_SDRAM                      0x40000000
88 #define PHYS_SDRAM_SIZE                 0x80000000
89
90 /* UART */
91 #define CONFIG_MXC_UART_BASE            UART2_BASE_ADDR
92
93 /* Monitor Command Prompt */
94 #define CONFIG_SYS_CBSIZE               SZ_2K
95 #define CONFIG_SYS_MAXARGS              64
96 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
97
98 /* USDHC */
99 #define CONFIG_FSL_USDHC
100 #define CONFIG_SYS_FSL_USDHC_NUM        2
101 #define CONFIG_SYS_FSL_ESDHC_ADDR       0
102 #define CONFIG_SYS_MMC_IMG_LOAD_PART    1
103
104 /* I2C */
105 #define CONFIG_SYS_I2C_SPEED            100000
106
107 #endif /* __PHYCORE_IMX8MP_H */