1 /* SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2019-2020 PHYTEC Messtechnik GmbH
4 * Author: Teresa Remmet <t.remmet@phytec.de>
7 #ifndef __PHYCORE_IMX8MM_H
8 #define __PHYCORE_IMX8MM_H
10 #include <linux/sizes.h>
11 #include <linux/stringify.h>
12 #include <asm/arch/imx-regs.h>
14 #define CONFIG_SYS_BOOTM_LEN SZ_64M
15 #define CONFIG_SYS_MONITOR_LEN SZ_512K
16 #define CONFIG_SYS_UBOOT_BASE \
17 (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
19 #ifdef CONFIG_SPL_BUILD
20 #define CONFIG_SPL_STACK 0x920000
21 #define CONFIG_SPL_BSS_START_ADDR 0x910000
22 #define CONFIG_SPL_BSS_MAX_SIZE SZ_8K
23 #define CONFIG_SYS_SPL_MALLOC_START 0x42200000
24 #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K
26 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
27 #define CONFIG_MALLOC_F_ADDR 0x930000
28 /* For RAW image gives a error info not panic */
29 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
32 #define CONFIG_EXTRA_ENV_SETTINGS \
34 "console=ttymxc2,115200\0" \
35 "fdt_addr=0x48000000\0" \
36 "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
38 "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
41 "mmcautodetect=yes\0" \
42 "mmcargs=setenv bootargs console=${console} " \
43 "root=/dev/mmcblk${mmcdev}p${mmcroot} rootwait rw\0" \
44 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
45 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
46 "mmcboot=echo Booting from mmc ...; " \
48 "if run loadfdt; then " \
49 "booti ${loadaddr} - ${fdt_addr}; " \
51 "echo WARN: Cannot load the DT; " \
54 "netargs=setenv bootargs console=${console} root=/dev/nfs ip=dhcp " \
55 "nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
56 "netboot=echo Booting from net ...; " \
58 "if test ${ip_dyn} = yes; then " \
59 "setenv get_cmd dhcp; " \
61 "setenv get_cmd tftp; " \
63 "${get_cmd} ${loadaddr} ${image}; " \
64 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
65 "booti ${loadaddr} - ${fdt_addr}; " \
67 "echo WARN: Cannot load the DT; " \
70 /* Link Definitions */
72 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
73 #define CONFIG_SYS_INIT_RAM_SIZE SZ_512K
74 #define CONFIG_SYS_INIT_SP_OFFSET \
75 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
76 #define CONFIG_SYS_INIT_SP_ADDR \
77 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
80 #define CONFIG_SYS_SDRAM_BASE 0x40000000
82 #define PHYS_SDRAM 0x40000000
83 #define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */
86 #define CONFIG_MXC_UART_BASE UART_BASE_ADDR(3)
88 #endif /* __PHYCORE_IMX8MM_H */