1 /* SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2019-2020 PHYTEC Messtechnik GmbH
4 * Author: Teresa Remmet <t.remmet@phytec.de>
7 #ifndef __PHYCORE_IMX8MM_H
8 #define __PHYCORE_IMX8MM_H
10 #include <linux/sizes.h>
11 #include <linux/stringify.h>
12 #include <asm/arch/imx-regs.h>
14 #define CONFIG_SYS_BOOTM_LEN SZ_64M
15 #define CONFIG_SYS_MONITOR_LEN SZ_512K
16 #define CONFIG_SYS_UBOOT_BASE \
17 (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
19 #ifdef CONFIG_SPL_BUILD
20 #define CONFIG_SYS_SPL_MALLOC_START 0x42200000
21 #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K
23 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
24 #define CONFIG_MALLOC_F_ADDR 0x930000
25 /* For RAW image gives a error info not panic */
26 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
29 #define CONFIG_EXTRA_ENV_SETTINGS \
31 "console=ttymxc2,115200\0" \
32 "fdt_addr=0x48000000\0" \
33 "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
35 "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
38 "mmcautodetect=yes\0" \
39 "mmcargs=setenv bootargs console=${console} " \
40 "root=/dev/mmcblk${mmcdev}p${mmcroot} rootwait rw\0" \
41 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
42 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
43 "mmcboot=echo Booting from mmc ...; " \
45 "if run loadfdt; then " \
46 "booti ${loadaddr} - ${fdt_addr}; " \
48 "echo WARN: Cannot load the DT; " \
51 "netargs=setenv bootargs console=${console} root=/dev/nfs ip=dhcp " \
52 "nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
53 "netboot=echo Booting from net ...; " \
55 "if test ${ip_dyn} = yes; then " \
56 "setenv get_cmd dhcp; " \
58 "setenv get_cmd tftp; " \
60 "${get_cmd} ${loadaddr} ${image}; " \
61 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
62 "booti ${loadaddr} - ${fdt_addr}; " \
64 "echo WARN: Cannot load the DT; " \
67 /* Link Definitions */
69 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
70 #define CONFIG_SYS_INIT_RAM_SIZE SZ_512K
73 #define CONFIG_SYS_SDRAM_BASE 0x40000000
75 #define PHYS_SDRAM 0x40000000
76 #define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */
79 #define CONFIG_MXC_UART_BASE UART_BASE_ADDR(3)
81 #endif /* __PHYCORE_IMX8MM_H */