1 /* SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2019-2020 PHYTEC Messtechnik GmbH
4 * Author: Teresa Remmet <t.remmet@phytec.de>
7 #ifndef __PHYCORE_IMX8MM_H
8 #define __PHYCORE_IMX8MM_H
10 #include <linux/sizes.h>
11 #include <linux/stringify.h>
12 #include <asm/arch/imx-regs.h>
14 #define CONFIG_SYS_BOOTM_LEN SZ_64M
15 #define CONFIG_SPL_MAX_SIZE (148 * SZ_1K)
16 #define CONFIG_SYS_MONITOR_LEN SZ_512K
17 #define CONFIG_SYS_UBOOT_BASE \
18 (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
20 #ifdef CONFIG_SPL_BUILD
21 #define CONFIG_SPL_STACK 0x920000
22 #define CONFIG_SPL_BSS_START_ADDR 0x910000
23 #define CONFIG_SPL_BSS_MAX_SIZE SZ_8K
24 #define CONFIG_SYS_SPL_MALLOC_START 0x42200000
25 #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K
27 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
28 #define CONFIG_MALLOC_F_ADDR 0x930000
29 /* For RAW image gives a error info not panic */
30 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
33 #define CONFIG_EXTRA_ENV_SETTINGS \
35 "console=ttymxc2,115200\0" \
36 "fdt_addr=0x48000000\0" \
37 "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
39 "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
42 "mmcautodetect=yes\0" \
43 "mmcargs=setenv bootargs console=${console} " \
44 "root=/dev/mmcblk${mmcdev}p${mmcroot} rootwait rw\0" \
45 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
46 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
47 "mmcboot=echo Booting from mmc ...; " \
49 "if run loadfdt; then " \
50 "booti ${loadaddr} - ${fdt_addr}; " \
52 "echo WARN: Cannot load the DT; " \
55 "netargs=setenv bootargs console=${console} root=/dev/nfs ip=dhcp " \
56 "nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
57 "netboot=echo Booting from net ...; " \
59 "if test ${ip_dyn} = yes; then " \
60 "setenv get_cmd dhcp; " \
62 "setenv get_cmd tftp; " \
64 "${get_cmd} ${loadaddr} ${image}; " \
65 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
66 "booti ${loadaddr} - ${fdt_addr}; " \
68 "echo WARN: Cannot load the DT; " \
71 /* Link Definitions */
73 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
74 #define CONFIG_SYS_INIT_RAM_SIZE SZ_512K
75 #define CONFIG_SYS_INIT_SP_OFFSET \
76 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
77 #define CONFIG_SYS_INIT_SP_ADDR \
78 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
80 #define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */
82 #define CONFIG_SYS_SDRAM_BASE 0x40000000
84 #define PHYS_SDRAM 0x40000000
85 #define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */
88 #define CONFIG_MXC_UART_BASE UART3_BASE_ADDR
90 /* Monitor Command Prompt */
91 #define CONFIG_SYS_CBSIZE SZ_2K
92 #define CONFIG_SYS_MAXARGS 64
93 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
96 #define CONFIG_SYS_FSL_USDHC_NUM 2
97 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
99 #endif /* __PHYCORE_IMX8MM_H */