1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2020 Hitachi ABB Power Grids
6 #ifndef __CONFIG_PG_WCOM_EXPU1_H
7 #define __CONFIG_PG_WCOM_EXPU1_H
10 #define CONFIG_HOSTNAME "EXPU1"
12 #define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0"
13 #define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
15 /* CLIPS FPGA Definitions */
16 #define CONFIG_SYS_CSPR3_EXT (0x00)
17 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CLIPS_BASE) | \
21 #define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
22 #define CONFIG_SYS_CSOR3 (CSOR_GPCM_ADM_SHIFT(0x4) | \
24 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \
25 FTIM0_GPCM_TEADC(0x7) | \
26 FTIM0_GPCM_TEAHC(0x2))
27 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
28 FTIM1_GPCM_TRAD(0x12))
29 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x3) | \
30 FTIM2_GPCM_TCH(0x1) | \
32 #define CONFIG_SYS_CS3_FTIM3 0x04000000
35 #define WCOM_CLIPS_RST 0
36 #define WCOM_QSFP_RST 1
37 #define WCOM_PHY_RST 2
38 #define WCOM_TMG_RST 3
39 #define KM_DBG_ETH_RST 15
41 /* QRIO GPIOs used for deblocking */
42 #define KM_I2C_DEBLOCK_PORT QRIO_GPIO_A
43 #define KM_I2C_DEBLOCK_SCL 20
44 #define KM_I2C_DEBLOCK_SDA 21
47 #define WCOM_ZL30343_CFG_ADDR 0xe8070000
48 #define WCOM_ZL30343_SPI_BUS 0
49 #define WCOM_ZL30343_CS 0
51 #include "km/pg-wcom-ls102xa.h"
53 #endif /* __CONFIG_PG_WCOM_EXPU1_H */