include/configs/pdm360ng.h

   1 /*
   2  * (C) Copyright 2009-2010
   3  * Michael Weiß, ifm ecomatic gmbh, michael.weiss@ifm.com
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * pdm360ng board configuration file
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 #define CONFIG_PDM360NG 1
  16
  17 /*
  18  * Memory map for the PDM360NG board:
  19  *
  20  * 0x0000_0000 - 0x1FFF_FFFF    DDR RAM (512 MB)
  21  * 0x2000_0000 - 0x3FFF_FFFF    reserved (DDR RAM (512 MB)
  22  * 0x5000_0000 - 0x5001_FFFF    SRAM (128 KB)
  23  * 0x5004_0000 - 0x5005_FFFF    MRAM (CS2) (128 KB)
  24  * 0x8000_0000 - 0x803F_FFFF    IMMR (4 MB)
  25  * 0xF000_0000 - 0xF7FF_FFFF    NOR FLASH (CS0) (128 MB)
  26  * 0xF800_0000 - 0xFFFF_FFFF    NOR FLASH (CS1) (128 MB) optional
  27  */
  28
  29 /*
  30  * High Level Configuration Options
  31  */
  32 #define CONFIG_E300             1       /* E300 Family */
  33 #define CONFIG_FSL_DIU_FB       1       /* FSL DIU */
  34
  35 #define CONFIG_SYS_TEXT_BASE    0xF0000000
  36
  37 /* Used for silent command in environment */
  38 #define CONFIG_SYS_DEVICE_NULLDEV
  39
  40 /* Video */
  41
  42 #if defined(CONFIG_VIDEO)
  43 #define CONFIG_VGA_AS_SINGLE_DEVICE
  44 #define CONFIG_SPLASH_SCREEN
  45 #define CONFIG_VIDEO_LOGO
  46 #define CONFIG_VIDEO_BMP_RLE8
  47 #endif
  48
  49 #define CONFIG_SYS_MPC512X_CLKIN        33333333        /* in Hz */
  50
  51 #define CONFIG_MISC_INIT_R
  52
  53 #define CONFIG_SYS_IMMR                 0x80000000
  54 #define CONFIG_SYS_DIU_ADDR             ((CONFIG_SYS_IMMR) + 0x2100)
  55
  56 /*
  57  * DDR Setup
  58  */
  59
  60 /* DDR is system memory */
  61 #define CONFIG_SYS_DDR_BASE             0x00000000
  62 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  63 #define CONFIG_SYS_MAX_RAM_SIZE         0x40000000
  64
  65 /* DDR pin mux and slew rate */
  66 #define CONFIG_SYS_IOCTRL_MUX_DDR       0x00000012
  67
  68 /* Manually set all parameters as there's no SPD etc. */
  69 /*
  70  * DDR Controller Configuration for Micron DDR2 SDRAM MT47H128M8-3
  71  *
  72  * SYS_CFG:
  73  *      [31:31] MDDRC Soft Reset:       Diabled
  74  *      [30:30] DRAM CKE pin:           Enabled
  75  *      [29:29] DRAM CLK:               Enabled
  76  *      [28:28] Command Mode:           Enabled (For initialization only)
  77  *      [27:25] DRAM Row Select:        dram_row[15:0] = magenta_address[25:10]
  78  *      [24:21] DRAM Bank Select:       dram_bank[1:0] = magenta_address[11:10]
  79  *      [20:19] Read Test:              DON'T USE
  80  *      [18:18] Self Refresh:           Enabled
  81  *      [17:17] 16bit Mode:             Disabled
  82  *      [16:13] Read Delay:             3
  83  *      [12:12] Half DQS Delay:         Disabled
  84  *      [11:11] Quarter DQS Delay:      Disabled
  85  *      [10:08] Write Delay:            2
  86  *      [07:07] Early ODT:              Disabled
  87  *      [06:06] On DIE Termination:     Enabled
  88  *      [05:05] FIFO Overflow Clear:    DON'T USE here
  89  *      [04:04] FIFO Underflow Clear:   DON'T USE here
  90  *      [03:03] FIFO Overflow Pending:  DON'T USE here
  91  *      [02:02] FIFO Underlfow Pending: DON'T USE here
  92  *      [01:01] FIFO Overlfow Enabled:  Enabled
  93  *      [00:00] FIFO Underflow Enabled: Enabled
  94  * TIME_CFG0
  95  *      [31:16] DRAM Refresh Time:      0 CSB clocks
  96  *      [15:8]  DRAM Command Time:      0 CSB clocks
  97  *      [07:00] DRAM Precharge Time:    0 CSB clocks
  98  * TIME_CFG1
  99  *      [31:26] DRAM tRFC:
 100  *      [25:21] DRAM tWR1:
 101  *      [20:17] DRAM tWRT1:
 102  *      [16:11] DRAM tDRR:
 103  *      [10:05] DRAM tRC:
 104  *      [04:00] DRAM tRAS:
 105  * TIME_CFG2
 106  *      [31:28] DRAM tRCD:
 107  *      [27:23] DRAM tFAW:
 108  *      [22:19] DRAM tRTW1:
 109  *      [18:15] DRAM tCCD:
 110  *      [14:10] DRAM tRTP:
 111  *      [09:05] DRAM tRP:
 112  *      [04:00] DRAM tRPA
 113  */
 114 #define CONFIG_SYS_MDDRC_SYS_CFG        0xEA804A40
 115 #define CONFIG_SYS_MDDRC_TIME_CFG0      0x030C3D2E
 116 #define CONFIG_SYS_MDDRC_TIME_CFG1      0x68EC1168
 117 #define CONFIG_SYS_MDDRC_TIME_CFG2      0x34310864
 118
 119 /*
 120  * Alternative 1: small RAM (128 MB) configuration
 121  */
 122 #define CONFIG_SYS_MDDRC_SYS_CFG_ALT1   0xE8604A40
 123 #define CONFIG_SYS_MDDRC_TIME_CFG0_ALT1 0x030C3D2E
 124 #define CONFIG_SYS_MDDRC_TIME_CFG1_ALT1 0x3CEC1168
 125 #define CONFIG_SYS_MDDRC_TIME_CFG2_ALT1 0x33310863
 126
 127 #define CONFIG_SYS_MDDRC_SYS_CFG_EN     0xF0000000
 128
 129 #define CONFIG_SYS_DDRCMD_NOP           0x01380000
 130 #define CONFIG_SYS_DDRCMD_PCHG_ALL      0x01100400
 131 #define CONFIG_SYS_DDRCMD_EM2           0x01020000  /* EMR2 */
 132 #define CONFIG_SYS_DDRCMD_EM3           0x01030000  /* EMR3 */
 133 /* EMR with 150 ohm ODT todo: verify */
 134 #define CONFIG_SYS_DDRCMD_EN_DLL        0x01010040
 135 #define CONFIG_SYS_DDRCMD_RES_DLL       0x01000100
 136 #define CONFIG_SYS_DDRCMD_RFSH          0x01080000
 137 #define CONFIG_SYS_MICRON_INIT_DEV_OP   0x01000432
 138 /* EMR with 150 ohm ODT todo: verify */
 139 #define CONFIG_SYS_DDRCMD_OCD_DEFAULT   0x010107C0
 140 /* EMR new command with 150 ohm ODT todo: verify */
 141 #define CONFIG_SYS_DDRCMD_OCD_EXIT      0x01010440
 142
 143 /* DDR Priority Manager Configuration */
 144 #define CONFIG_SYS_MDDRCGRP_PM_CFG1     0x00077777
 145 #define CONFIG_SYS_MDDRCGRP_PM_CFG2     0x00000000
 146 #define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG  0x00000001
 147 #define CONFIG_SYS_MDDRCGRP_LUT0_MU     0xFFEEDDCC
 148 #define CONFIG_SYS_MDDRCGRP_LUT0_ML     0xBBAAAAAA
 149 #define CONFIG_SYS_MDDRCGRP_LUT1_MU     0x66666666
 150 #define CONFIG_SYS_MDDRCGRP_LUT1_ML     0x55555555
 151 #define CONFIG_SYS_MDDRCGRP_LUT2_MU     0x44444444
 152 #define CONFIG_SYS_MDDRCGRP_LUT2_ML     0x44444444
 153 #define CONFIG_SYS_MDDRCGRP_LUT3_MU     0x55555555
 154 #define CONFIG_SYS_MDDRCGRP_LUT3_ML     0x55555558
 155 #define CONFIG_SYS_MDDRCGRP_LUT4_MU     0x11111111
 156 #define CONFIG_SYS_MDDRCGRP_LUT4_ML     0x11111122
 157 #define CONFIG_SYS_MDDRCGRP_LUT0_AU     0xaaaaaaaa
 158 #define CONFIG_SYS_MDDRCGRP_LUT0_AL     0xaaaaaaaa
 159 #define CONFIG_SYS_MDDRCGRP_LUT1_AU     0x66666666
 160 #define CONFIG_SYS_MDDRCGRP_LUT1_AL     0x66666666
 161 #define CONFIG_SYS_MDDRCGRP_LUT2_AU     0x11111111
 162 #define CONFIG_SYS_MDDRCGRP_LUT2_AL     0x11111111
 163 #define CONFIG_SYS_MDDRCGRP_LUT3_AU     0x11111111
 164 #define CONFIG_SYS_MDDRCGRP_LUT3_AL     0x11111111
 165 #define CONFIG_SYS_MDDRCGRP_LUT4_AU     0x11111111
 166 #define CONFIG_SYS_MDDRCGRP_LUT4_AL     0x11111111
 167
 168 /*
 169  * NOR FLASH on the Local Bus
 170  */
 171 #define CONFIG_SYS_FLASH_CFI            /* use Common Flash Interface */
 172 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
 173 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 174
 175 #define CONFIG_SYS_FLASH_BASE           0xF0000000 /* start of FLASH-Bank0 */
 176 #define CONFIG_SYS_FLASH_SIZE           0x08000000 /* max size of a Bank */
 177 /* start of FLASH-Bank1 */
 178 #define CONFIG_SYS_FLASH1_BASE          (CONFIG_SYS_FLASH_BASE + \
 179                                          CONFIG_SYS_FLASH_SIZE)
 180 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max sectors per device */
 181 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 182 #define CONFIG_SYS_FLASH_BANKS_LIST \
 183         {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH1_BASE}
 184
 185 #define CONFIG_SYS_SRAM_BASE            0x50000000
 186 #define CONFIG_SYS_SRAM_SIZE            0x00020000      /* 128 KB */
 187
 188 #define CONFIG_SYS_CS1_START            CONFIG_SYS_FLASH1_BASE
 189 #define CONFIG_SYS_CS1_SIZE             CONFIG_SYS_FLASH_SIZE
 190
 191 /* ALE active low, data size 4 bytes */
 192 #define CONFIG_SYS_CS0_CFG              0x05059350
 193 /* ALE active low, data size 4 bytes */
 194 #define CONFIG_SYS_CS1_CFG              0x05059350
 195
 196 #define CONFIG_SYS_MRAM_BASE            0x50040000
 197 #define CONFIG_SYS_MRAM_SIZE            0x00020000
 198 #define CONFIG_SYS_CS2_START            CONFIG_SYS_MRAM_BASE
 199 #define CONFIG_SYS_CS2_SIZE             CONFIG_SYS_MRAM_SIZE
 200
 201 /* ALE active low, data size 4 bytes */
 202 #define CONFIG_SYS_CS2_CFG              0x05059110
 203
 204 /* alt. CS timing for CS0, CS1, CS2 */
 205 #define CONFIG_SYS_CS_ALETIMING         0x00000007
 206
 207 /*
 208  * NAND FLASH
 209  */
 210 #define CONFIG_CMD_NAND                 /* enable NAND support */
 211 #define CONFIG_NAND_MPC5121_NFC
 212 #define CONFIG_SYS_NAND_BASE            0x40000000
 213 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 214 #define CONFIG_SYS_NAND_SELECT_DEVICE   /* driver supports mutipl. chips */
 215
 216 /*
 217  * Configuration parameters for MPC5121 NAND driver
 218  */
 219 #define CONFIG_FSL_NFC_WIDTH 1
 220 #define CONFIG_FSL_NFC_WRITE_SIZE 2048
 221 #define CONFIG_FSL_NFC_SPARE_SIZE 64
 222 #define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
 223
 224 /*
 225  * Dynamic MTD partition support
 226  */
 227 #define CONFIG_CMD_MTDPARTS
 228 #define CONFIG_MTD_DEVICE       /* needed for mtdparts commands */
 229 #define CONFIG_FLASH_CFI_MTD
 230 #define MTDIDS_DEFAULT          "nor0=f0000000.flash,nor1=f8000000.flash," \
 231                                                 "nand0=MPC5121 NAND"
 232
 233 /*
 234  * Flash layout
 235  */
 236 #define MTDPARTS_DEFAULT        "mtdparts=f0000000.flash:512k(u-boot)," \
 237                                                 "256k(environment1),"   \
 238                                                 "256k(environment2),"   \
 239                                                 "256k(splash-factory)," \
 240                                                 "2m(FIT: recovery),"    \
 241                                                 "4608k(fs-recovery),"   \
 242                                                 "256k(splash-customer),"\
 243                                                 "5m(FIT: kernel+dtb),"  \
 244                                                 "64m(rootfs squash)ro," \
 245                                                 "51m(userfs ubi);"      \
 246                                         "f8000000.flash:-(unused);"     \
 247                                         "MPC5121 NAND:1024m(extended-userfs)"
 248
 249 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* Start of monitor */
 250 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* 512 kB for monitor */
 251 #ifdef  CONFIG_FSL_DIU_FB
 252 #define CONFIG_SYS_MALLOC_LEN           (6 * 1024 * 1024) /* for malloc */
 253 #else
 254 #define CONFIG_SYS_MALLOC_LEN           (512 * 1024)
 255 #endif
 256
 257 /*
 258  * Serial Port
 259  */
 260 #define CONFIG_CONS_INDEX     1
 261
 262 /*
 263  * Serial console configuration
 264  */
 265 #define CONFIG_PSC_CONSOLE      6       /* console is on PSC6 */
 266 #if CONFIG_PSC_CONSOLE != 6
 267 #error CONFIG_PSC_CONSOLE must be 6
 268 #endif
 269
 270 #define CONSOLE_FIFO_TX_SIZE    FIFOC_PSC6_TX_SIZE
 271 #define CONSOLE_FIFO_TX_ADDR    FIFOC_PSC6_TX_ADDR
 272 #define CONSOLE_FIFO_RX_SIZE    FIFOC_PSC6_RX_SIZE
 273 #define CONSOLE_FIFO_RX_ADDR    FIFOC_PSC6_RX_ADDR
 274
 275 /*
 276  * Clocks in use
 277  */
 278 #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN |                           \
 279                          CLOCK_SCCR1_LPC_EN |                           \
 280                          CLOCK_SCCR1_NFC_EN |                           \
 281                          CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |       \
 282                          CLOCK_SCCR1_PSCFIFO_EN |                       \
 283                          CLOCK_SCCR1_DDR_EN |                           \
 284                          CLOCK_SCCR1_FEC_EN |                           \
 285                          CLOCK_SCCR1_TPR_EN)
 286
 287 #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN |           \
 288                          CLOCK_SCCR2_SPDIF_EN |         \
 289                          CLOCK_SCCR2_DIU_EN |           \
 290                          CLOCK_SCCR2_I2C_EN)
 291
 292 /*
 293  * Used PSC UART devices
 294  */
 295 #define CONFIG_SYS_PSC1
 296 #define CONFIG_SYS_PSC4
 297 #define CONFIG_SYS_PSC6
 298
 299 /*
 300  * Co-processor communication parameters
 301  */
 302 #define CONFIG_SYS_PDM360NG_COPROC_READ_DELAY   5000
 303 #define CONFIG_SYS_PDM360NG_COPROC_BAUDRATE     38400
 304
 305 /*
 306  * I2C
 307  */
 308 #define CONFIG_HARD_I2C                 /* I2C with hardware support */
 309 #define CONFIG_I2C_MULTI_BUS
 310 #define CONFIG_I2C_CMD_TREE
 311 /* I2C speed and slave address */
 312 #define CONFIG_SYS_I2C_SPEED            100000
 313 #define CONFIG_SYS_I2C_SLAVE            0x7F
 314
 315 /*
 316  * IIM - IC Identification Module
 317  */
 318 #undef CONFIG_FSL_IIM
 319
 320 /*
 321  * EEPROM configuration
 322  */
 323 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2       /* 16-bit EEPROM addr */
 324 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* ST AT24C01 */
 325 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* 10ms of delay */
 326 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4       /* 16-Byte Write Mode */
 327
 328 /*
 329  * MAC addr in EEPROM
 330  */
 331 #define CONFIG_SYS_I2C_EEPROM_BUS_NUM           0
 332 #define CONFIG_SYS_I2C_EEPROM_MAC_OFFSET        0x10
 333 /*
 334  * Enabled only to delete "ethaddr" before testing
 335  * "ethaddr" setting from EEPROM
 336  */
 337 #define CONFIG_ENV_OVERWRITE
 338
 339 /*
 340  * Ethernet configuration
 341  */
 342 #define CONFIG_MPC512x_FEC      1
 343 #define CONFIG_PHY_ADDR         0x1F
 344 #define CONFIG_MII              1       /* MII PHY management   */
 345 #define CONFIG_FEC_AN_TIMEOUT   1
 346 #define CONFIG_HAS_ETH0
 347
 348 /*
 349  * Configure on-board RTC
 350  */
 351 #define CONFIG_RTC_M41T62                       /* use M41T00 rtc via i2c */
 352 #define CONFIG_SYS_I2C_RTC_ADDR         0x68    /* at address 0x68      */
 353
 354 /*
 355  * Environment
 356  */
 357 #define CONFIG_ENV_IS_IN_FLASH  1
 358 /* This has to be a multiple of the Flash sector size */
 359 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 360                                  CONFIG_SYS_MONITOR_LEN)
 361 #define CONFIG_ENV_SIZE         0x2000
 362 #define CONFIG_ENV_SECT_SIZE    0x40000         /* one sector (256K) for env */
 363
 364 /* Address and size of Redundant Environment Sector     */
 365 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 366 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 367
 368 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 369 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 370
 371 #define CONFIG_CMD_DATE
 372 #define CONFIG_CMD_EEPROM
 373 #define CONFIG_CMD_REGINFO
 374
 375 #undef CONFIG_CMD_FUSE
 376
 377 #ifdef CONFIG_VIDEO
 378 #define CONFIG_CMD_BMP
 379 #endif
 380
 381 /*
 382  * Miscellaneous configurable options
 383  */
 384 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 385 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 386
 387 #ifdef CONFIG_CMD_KGDB
 388         #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size */
 389 #else
 390         #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
 391 #endif
 392
 393 /* Print Buffer Size */
 394 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 395 /* Max number of command args */
 396 #define CONFIG_SYS_MAXARGS      16
 397 /* Boot Argument Buffer Size */
 398 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 399 /* Decrementer freq: 1ms ticks */
 400
 401 /*
 402  * For booting Linux, the board info and command line data
 403  * have to be in the first 256 MB of memory, since this is
 404  * the maximum mapped by the Linux kernel during initialization.
 405  */
 406 /* Initial Memory map for Linux */
 407 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 408
 409 /* Cache Configuration */
 410 #define CONFIG_SYS_DCACHE_SIZE          32768
 411 #define CONFIG_SYS_CACHELINE_SIZE       32
 412 #ifdef CONFIG_CMD_KGDB
 413 /* log base 2 of the above value */
 414 #define CONFIG_SYS_CACHELINE_SHIFT      5
 415 #endif
 416
 417 #define CONFIG_SYS_HID0_INIT    0x000000000
 418 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | HID0_ICE)
 419 #define CONFIG_SYS_HID2 HID2_HBE
 420
 421 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 422
 423 #ifdef CONFIG_CMD_KGDB
 424 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 425 #endif
 426
 427 /* POST support */
 428 #define CONFIG_POST             (CONFIG_SYS_POST_COPROC)
 429
 430 /*
 431  * Environment Configuration
 432  */
 433 #define CONFIG_TIMESTAMP
 434
 435 #define CONFIG_HOSTNAME         pdm360ng
 436 /* default location for tftp and bootm */
 437 #define CONFIG_LOADADDR         400000
 438
 439
 440 #define CONFIG_PREBOOT  "echo;" \
 441         "echo PDM360NG SAMPLE;" \
 442         "echo"
 443
 444 #define CONFIG_BOOTCOMMAND      "run env_cont"
 445
 446 #define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES      1
 447
 448 #define OF_CPU                  "PowerPC,5121@0"
 449 #define OF_SOC_COMPAT           "fsl,mpc5121-immr"
 450 #define OF_TBCLK                (bd->bi_busfreq / 4)
 451 #define OF_STDOUT_PATH          "/soc@80000000/serial@11600"
 452
 453 /*
 454  * Include common options for all mpc5121 boards
 455  */
 456 #include "mpc5121-common.h"
 457
 458 #endif  /* __CONFIG_H */