Merge branch 'u-boot-arm/next' into 'u-boot-arm/master'
[platform/kernel/u-boot.git] / include / configs / pdm360ng.h
1 /*
2  * (C) Copyright 2009-2010
3  * Michael Weiß, ifm ecomatic gmbh, michael.weiss@ifm.com
4  *
5  * SPDX-License-Identifier:     GPL-2.0+
6  */
7
8 /*
9  * pdm360ng board configuration file
10  */
11
12 #ifndef __CONFIG_H
13 #define __CONFIG_H
14
15 #define CONFIG_PDM360NG 1
16
17 /*
18  * Memory map for the PDM360NG board:
19  *
20  * 0x0000_0000 - 0x1FFF_FFFF    DDR RAM (512 MB)
21  * 0x2000_0000 - 0x3FFF_FFFF    reserved (DDR RAM (512 MB)
22  * 0x5000_0000 - 0x5001_FFFF    SRAM (128 KB)
23  * 0x5004_0000 - 0x5005_FFFF    MRAM (CS2) (128 KB)
24  * 0x8000_0000 - 0x803F_FFFF    IMMR (4 MB)
25  * 0xF000_0000 - 0xF7FF_FFFF    NOR FLASH (CS0) (128 MB)
26  * 0xF800_0000 - 0xFFFF_FFFF    NOR FLASH (CS1) (128 MB) optional
27  */
28
29 /*
30  * High Level Configuration Options
31  */
32 #define CONFIG_E300             1       /* E300 Family */
33 #define CONFIG_FSL_DIU_FB       1       /* FSL DIU */
34
35 #define CONFIG_SYS_TEXT_BASE    0xF0000000
36
37 /* Used for silent command in environment */
38 #define CONFIG_SYS_DEVICE_NULLDEV
39 #define CONFIG_SILENT_CONSOLE
40
41 /* Video */
42 #define CONFIG_VIDEO
43
44 #if defined(CONFIG_VIDEO)
45 #define CONFIG_CFB_CONSOLE
46 #define CONFIG_VGA_AS_SINGLE_DEVICE
47 #define CONFIG_SPLASH_SCREEN
48 #define CONFIG_VIDEO_LOGO
49 #define CONFIG_VIDEO_BMP_RLE8
50 #endif
51
52 #define CONFIG_SYS_MPC512X_CLKIN        33333333        /* in Hz */
53
54 #define CONFIG_MISC_INIT_R
55
56 #define CONFIG_SYS_IMMR                 0x80000000
57 #define CONFIG_SYS_DIU_ADDR             ((CONFIG_SYS_IMMR) + 0x2100)
58
59 /*
60  * DDR Setup
61  */
62
63 /* DDR is system memory */
64 #define CONFIG_SYS_DDR_BASE             0x00000000
65 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
66 #define CONFIG_SYS_MAX_RAM_SIZE         0x40000000
67
68 /* DDR pin mux and slew rate */
69 #define CONFIG_SYS_IOCTRL_MUX_DDR       0x00000012
70
71 /* Manually set all parameters as there's no SPD etc. */
72 /*
73  * DDR Controller Configuration for Micron DDR2 SDRAM MT47H128M8-3
74  *
75  * SYS_CFG:
76  *      [31:31] MDDRC Soft Reset:       Diabled
77  *      [30:30] DRAM CKE pin:           Enabled
78  *      [29:29] DRAM CLK:               Enabled
79  *      [28:28] Command Mode:           Enabled (For initialization only)
80  *      [27:25] DRAM Row Select:        dram_row[15:0] = magenta_address[25:10]
81  *      [24:21] DRAM Bank Select:       dram_bank[1:0] = magenta_address[11:10]
82  *      [20:19] Read Test:              DON'T USE
83  *      [18:18] Self Refresh:           Enabled
84  *      [17:17] 16bit Mode:             Disabled
85  *      [16:13] Read Delay:             3
86  *      [12:12] Half DQS Delay:         Disabled
87  *      [11:11] Quarter DQS Delay:      Disabled
88  *      [10:08] Write Delay:            2
89  *      [07:07] Early ODT:              Disabled
90  *      [06:06] On DIE Termination:     Enabled
91  *      [05:05] FIFO Overflow Clear:    DON'T USE here
92  *      [04:04] FIFO Underflow Clear:   DON'T USE here
93  *      [03:03] FIFO Overflow Pending:  DON'T USE here
94  *      [02:02] FIFO Underlfow Pending: DON'T USE here
95  *      [01:01] FIFO Overlfow Enabled:  Enabled
96  *      [00:00] FIFO Underflow Enabled: Enabled
97  * TIME_CFG0
98  *      [31:16] DRAM Refresh Time:      0 CSB clocks
99  *      [15:8]  DRAM Command Time:      0 CSB clocks
100  *      [07:00] DRAM Precharge Time:    0 CSB clocks
101  * TIME_CFG1
102  *      [31:26] DRAM tRFC:
103  *      [25:21] DRAM tWR1:
104  *      [20:17] DRAM tWRT1:
105  *      [16:11] DRAM tDRR:
106  *      [10:05] DRAM tRC:
107  *      [04:00] DRAM tRAS:
108  * TIME_CFG2
109  *      [31:28] DRAM tRCD:
110  *      [27:23] DRAM tFAW:
111  *      [22:19] DRAM tRTW1:
112  *      [18:15] DRAM tCCD:
113  *      [14:10] DRAM tRTP:
114  *      [09:05] DRAM tRP:
115  *      [04:00] DRAM tRPA
116  */
117 #define CONFIG_SYS_MDDRC_SYS_CFG        0xEA804A40
118 #define CONFIG_SYS_MDDRC_TIME_CFG0      0x030C3D2E
119 #define CONFIG_SYS_MDDRC_TIME_CFG1      0x68EC1168
120 #define CONFIG_SYS_MDDRC_TIME_CFG2      0x34310864
121
122 /*
123  * Alternative 1: small RAM (128 MB) configuration
124  */
125 #define CONFIG_SYS_MDDRC_SYS_CFG_ALT1   0xE8604A40
126 #define CONFIG_SYS_MDDRC_TIME_CFG0_ALT1 0x030C3D2E
127 #define CONFIG_SYS_MDDRC_TIME_CFG1_ALT1 0x3CEC1168
128 #define CONFIG_SYS_MDDRC_TIME_CFG2_ALT1 0x33310863
129
130 #define CONFIG_SYS_MDDRC_SYS_CFG_EN     0xF0000000
131
132 #define CONFIG_SYS_DDRCMD_NOP           0x01380000
133 #define CONFIG_SYS_DDRCMD_PCHG_ALL      0x01100400
134 #define CONFIG_SYS_DDRCMD_EM2           0x01020000  /* EMR2 */
135 #define CONFIG_SYS_DDRCMD_EM3           0x01030000  /* EMR3 */
136 /* EMR with 150 ohm ODT todo: verify */
137 #define CONFIG_SYS_DDRCMD_EN_DLL        0x01010040
138 #define CONFIG_SYS_DDRCMD_RES_DLL       0x01000100
139 #define CONFIG_SYS_DDRCMD_RFSH          0x01080000
140 #define CONFIG_SYS_MICRON_INIT_DEV_OP   0x01000432
141 /* EMR with 150 ohm ODT todo: verify */
142 #define CONFIG_SYS_DDRCMD_OCD_DEFAULT   0x010107C0
143 /* EMR new command with 150 ohm ODT todo: verify */
144 #define CONFIG_SYS_DDRCMD_OCD_EXIT      0x01010440
145
146 /* DDR Priority Manager Configuration */
147 #define CONFIG_SYS_MDDRCGRP_PM_CFG1     0x00077777
148 #define CONFIG_SYS_MDDRCGRP_PM_CFG2     0x00000000
149 #define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG  0x00000001
150 #define CONFIG_SYS_MDDRCGRP_LUT0_MU     0xFFEEDDCC
151 #define CONFIG_SYS_MDDRCGRP_LUT0_ML     0xBBAAAAAA
152 #define CONFIG_SYS_MDDRCGRP_LUT1_MU     0x66666666
153 #define CONFIG_SYS_MDDRCGRP_LUT1_ML     0x55555555
154 #define CONFIG_SYS_MDDRCGRP_LUT2_MU     0x44444444
155 #define CONFIG_SYS_MDDRCGRP_LUT2_ML     0x44444444
156 #define CONFIG_SYS_MDDRCGRP_LUT3_MU     0x55555555
157 #define CONFIG_SYS_MDDRCGRP_LUT3_ML     0x55555558
158 #define CONFIG_SYS_MDDRCGRP_LUT4_MU     0x11111111
159 #define CONFIG_SYS_MDDRCGRP_LUT4_ML     0x11111122
160 #define CONFIG_SYS_MDDRCGRP_LUT0_AU     0xaaaaaaaa
161 #define CONFIG_SYS_MDDRCGRP_LUT0_AL     0xaaaaaaaa
162 #define CONFIG_SYS_MDDRCGRP_LUT1_AU     0x66666666
163 #define CONFIG_SYS_MDDRCGRP_LUT1_AL     0x66666666
164 #define CONFIG_SYS_MDDRCGRP_LUT2_AU     0x11111111
165 #define CONFIG_SYS_MDDRCGRP_LUT2_AL     0x11111111
166 #define CONFIG_SYS_MDDRCGRP_LUT3_AU     0x11111111
167 #define CONFIG_SYS_MDDRCGRP_LUT3_AL     0x11111111
168 #define CONFIG_SYS_MDDRCGRP_LUT4_AU     0x11111111
169 #define CONFIG_SYS_MDDRCGRP_LUT4_AL     0x11111111
170
171 /*
172  * NOR FLASH on the Local Bus
173  */
174 #define CONFIG_SYS_FLASH_CFI            /* use Common Flash Interface */
175 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
176 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
177
178 #define CONFIG_SYS_FLASH_BASE           0xF0000000 /* start of FLASH-Bank0 */
179 #define CONFIG_SYS_FLASH_SIZE           0x08000000 /* max size of a Bank */
180 /* start of FLASH-Bank1 */
181 #define CONFIG_SYS_FLASH1_BASE          (CONFIG_SYS_FLASH_BASE + \
182                                          CONFIG_SYS_FLASH_SIZE)
183 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max sectors per device */
184 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
185 #define CONFIG_SYS_FLASH_BANKS_LIST \
186         {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH1_BASE}
187
188 #define CONFIG_SYS_SRAM_BASE            0x50000000
189 #define CONFIG_SYS_SRAM_SIZE            0x00020000      /* 128 KB */
190
191 #define CONFIG_SYS_CS1_START            CONFIG_SYS_FLASH1_BASE
192 #define CONFIG_SYS_CS1_SIZE             CONFIG_SYS_FLASH_SIZE
193
194 /* ALE active low, data size 4 bytes */
195 #define CONFIG_SYS_CS0_CFG              0x05059350
196 /* ALE active low, data size 4 bytes */
197 #define CONFIG_SYS_CS1_CFG              0x05059350
198
199 #define CONFIG_SYS_MRAM_BASE            0x50040000
200 #define CONFIG_SYS_MRAM_SIZE            0x00020000
201 #define CONFIG_SYS_CS2_START            CONFIG_SYS_MRAM_BASE
202 #define CONFIG_SYS_CS2_SIZE             CONFIG_SYS_MRAM_SIZE
203
204 /* ALE active low, data size 4 bytes */
205 #define CONFIG_SYS_CS2_CFG              0x05059110
206
207 /* alt. CS timing for CS0, CS1, CS2 */
208 #define CONFIG_SYS_CS_ALETIMING         0x00000007
209
210 /*
211  * NAND FLASH
212  */
213 #define CONFIG_CMD_NAND                 /* enable NAND support */
214 #define CONFIG_NAND_MPC5121_NFC
215 #define CONFIG_SYS_NAND_BASE            0x40000000
216 #define CONFIG_SYS_MAX_NAND_DEVICE      1
217 #define CONFIG_SYS_NAND_SELECT_DEVICE   /* driver supports mutipl. chips */
218
219 /*
220  * Configuration parameters for MPC5121 NAND driver
221  */
222 #define CONFIG_FSL_NFC_WIDTH 1
223 #define CONFIG_FSL_NFC_WRITE_SIZE 2048
224 #define CONFIG_FSL_NFC_SPARE_SIZE 64
225 #define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
226
227 /*
228  * Dynamic MTD partition support
229  */
230 #define CONFIG_CMD_MTDPARTS
231 #define CONFIG_MTD_DEVICE       /* needed for mtdparts commands */
232 #define CONFIG_FLASH_CFI_MTD
233 #define MTDIDS_DEFAULT          "nor0=f0000000.flash,nor1=f8000000.flash," \
234                                                 "nand0=MPC5121 NAND"
235
236 /*
237  * Flash layout
238  */
239 #define MTDPARTS_DEFAULT        "mtdparts=f0000000.flash:512k(u-boot)," \
240                                                 "256k(environment1),"   \
241                                                 "256k(environment2),"   \
242                                                 "256k(splash-factory)," \
243                                                 "2m(FIT: recovery),"    \
244                                                 "4608k(fs-recovery),"   \
245                                                 "256k(splash-customer),"\
246                                                 "5m(FIT: kernel+dtb),"  \
247                                                 "64m(rootfs squash)ro," \
248                                                 "51m(userfs ubi);"      \
249                                         "f8000000.flash:-(unused);"     \
250                                         "MPC5121 NAND:1024m(extended-userfs)"
251
252 /*
253  * Override partitions in device tree using info
254  * in "mtdparts" environment variable
255  */
256 #ifdef CONFIG_CMD_MTDPARTS
257 #define CONFIG_FDT_FIXUP_PARTITIONS
258 #endif
259
260 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* Start of monitor */
261 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* 512 kB for monitor */
262 #ifdef  CONFIG_FSL_DIU_FB
263 #define CONFIG_SYS_MALLOC_LEN           (6 * 1024 * 1024) /* for malloc */
264 #else
265 #define CONFIG_SYS_MALLOC_LEN           (512 * 1024)
266 #endif
267
268 /*
269  * Serial Port
270  */
271 #define CONFIG_CONS_INDEX     1
272
273 /*
274  * Serial console configuration
275  */
276 #define CONFIG_PSC_CONSOLE      6       /* console is on PSC6 */
277 #if CONFIG_PSC_CONSOLE != 6
278 #error CONFIG_PSC_CONSOLE must be 6
279 #endif
280
281 #define CONSOLE_FIFO_TX_SIZE    FIFOC_PSC6_TX_SIZE
282 #define CONSOLE_FIFO_TX_ADDR    FIFOC_PSC6_TX_ADDR
283 #define CONSOLE_FIFO_RX_SIZE    FIFOC_PSC6_RX_SIZE
284 #define CONSOLE_FIFO_RX_ADDR    FIFOC_PSC6_RX_ADDR
285
286 /*
287  * Clocks in use
288  */
289 #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN |                           \
290                          CLOCK_SCCR1_LPC_EN |                           \
291                          CLOCK_SCCR1_NFC_EN |                           \
292                          CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |       \
293                          CLOCK_SCCR1_PSCFIFO_EN |                       \
294                          CLOCK_SCCR1_DDR_EN |                           \
295                          CLOCK_SCCR1_FEC_EN |                           \
296                          CLOCK_SCCR1_TPR_EN)
297
298 #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN |           \
299                          CLOCK_SCCR2_SPDIF_EN |         \
300                          CLOCK_SCCR2_DIU_EN |           \
301                          CLOCK_SCCR2_I2C_EN)
302
303 /*
304  * Used PSC UART devices
305  */
306 #define CONFIG_SYS_PSC1
307 #define CONFIG_SYS_PSC4
308 #define CONFIG_SYS_PSC6
309
310 /*
311  * Co-processor communication parameters
312  */
313 #define CONFIG_SYS_PDM360NG_COPROC_READ_DELAY   5000
314 #define CONFIG_SYS_PDM360NG_COPROC_BAUDRATE     38400
315
316 /*
317  * I2C
318  */
319 #define CONFIG_HARD_I2C                 /* I2C with hardware support */
320 #define CONFIG_I2C_MULTI_BUS
321 #define CONFIG_I2C_CMD_TREE
322 /* I2C speed and slave address */
323 #define CONFIG_SYS_I2C_SPEED            100000
324 #define CONFIG_SYS_I2C_SLAVE            0x7F
325
326 /*
327  * IIM - IC Identification Module
328  */
329 #undef CONFIG_FSL_IIM
330
331 /*
332  * EEPROM configuration
333  */
334 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2       /* 16-bit EEPROM addr */
335 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* ST AT24C01 */
336 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* 10ms of delay */
337 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4       /* 16-Byte Write Mode */
338
339 /*
340  * MAC addr in EEPROM
341  */
342 #define CONFIG_SYS_I2C_EEPROM_BUS_NUM           0
343 #define CONFIG_SYS_I2C_EEPROM_MAC_OFFSET        0x10
344 /*
345  * Enabled only to delete "ethaddr" before testing
346  * "ethaddr" setting from EEPROM
347  */
348 #define CONFIG_ENV_OVERWRITE
349
350 /*
351  * Ethernet configuration
352  */
353 #define CONFIG_MPC512x_FEC      1
354 #define CONFIG_PHY_ADDR         0x1F
355 #define CONFIG_MII              1       /* MII PHY management   */
356 #define CONFIG_FEC_AN_TIMEOUT   1
357 #define CONFIG_HAS_ETH0
358
359 /*
360  * Configure on-board RTC
361  */
362 #define CONFIG_RTC_M41T62                       /* use M41T00 rtc via i2c */
363 #define CONFIG_SYS_I2C_RTC_ADDR         0x68    /* at address 0x68      */
364
365 /*
366  * Environment
367  */
368 #define CONFIG_ENV_IS_IN_FLASH  1
369 /* This has to be a multiple of the Flash sector size */
370 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
371                                  CONFIG_SYS_MONITOR_LEN)
372 #define CONFIG_ENV_SIZE         0x2000
373 #define CONFIG_ENV_SECT_SIZE    0x40000         /* one sector (256K) for env */
374
375 /* Address and size of Redundant Environment Sector     */
376 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
377 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
378
379 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
380 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
381
382 #include <config_cmd_default.h>
383
384 #define CONFIG_CMD_ASKENV
385 #define CONFIG_CMD_DATE
386 #define CONFIG_CMD_DHCP
387 #define CONFIG_CMD_EEPROM
388 #define CONFIG_CMD_I2C
389 #define CONFIG_CMD_MII
390 #define CONFIG_CMD_PING
391 #define CONFIG_CMD_REGINFO
392
393 #undef CONFIG_CMD_FUSE
394
395 #ifdef CONFIG_VIDEO
396 #define CONFIG_CMD_BMP
397 #endif
398
399 /*
400  * Miscellaneous configurable options
401  */
402 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
403 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
404
405 #ifdef CONFIG_CMD_KGDB
406         #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size */
407 #else
408         #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
409 #endif
410
411 /* Print Buffer Size */
412 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
413 /* Max number of command args */
414 #define CONFIG_SYS_MAXARGS      16
415 /* Boot Argument Buffer Size */
416 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
417 /* Decrementer freq: 1ms ticks */
418
419 /*
420  * For booting Linux, the board info and command line data
421  * have to be in the first 256 MB of memory, since this is
422  * the maximum mapped by the Linux kernel during initialization.
423  */
424 /* Initial Memory map for Linux */
425 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
426
427 /* Cache Configuration */
428 #define CONFIG_SYS_DCACHE_SIZE          32768
429 #define CONFIG_SYS_CACHELINE_SIZE       32
430 #ifdef CONFIG_CMD_KGDB
431 /* log base 2 of the above value */
432 #define CONFIG_SYS_CACHELINE_SHIFT      5
433 #endif
434
435 #define CONFIG_SYS_HID0_INIT    0x000000000
436 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | HID0_ICE)
437 #define CONFIG_SYS_HID2 HID2_HBE
438
439 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
440
441 #ifdef CONFIG_CMD_KGDB
442 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
443 #endif
444
445 /* POST support */
446 #define CONFIG_POST             (CONFIG_SYS_POST_COPROC)
447
448 /*
449  * Environment Configuration
450  */
451 #define CONFIG_TIMESTAMP
452
453 #define CONFIG_HOSTNAME         pdm360ng
454 /* default location for tftp and bootm */
455 #define CONFIG_LOADADDR         400000
456
457 #define CONFIG_BOOTDELAY        5       /* -1 disables auto-boot */
458
459 #define CONFIG_PREBOOT  "echo;" \
460         "echo PDM360NG SAMPLE;" \
461         "echo"
462
463 #define CONFIG_BOOTCOMMAND      "run env_cont"
464
465 #define CONFIG_OF_LIBFDT        1
466 #define CONFIG_OF_BOARD_SETUP   1
467 #define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES      1
468 #define CONFIG_FIT
469 #define CONFIG_FIT_VERBOSE
470
471 #define OF_CPU                  "PowerPC,5121@0"
472 #define OF_SOC_COMPAT           "fsl,mpc5121-immr"
473 #define OF_TBCLK                (bd->bi_busfreq / 4)
474 #define OF_STDOUT_PATH          "/soc@80000000/serial@11600"
475
476 /*
477  * Include common options for all mpc5121 boards
478  */
479 #include "mpc5121-common.h"
480
481 #endif  /* __CONFIG_H */