1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) Stefano Babic <sbabic@denx.de>
7 #ifndef __PCM058_CONFIG_H
8 #define __PCM058_CONFIG_H
14 #include "mx6_common.h"
17 #define CONFIG_IMX_THERMAL
20 #define CONFIG_MXC_UART
21 #define CONFIG_MXC_UART_BASE UART2_BASE
22 #define CONSOLE_DEV "ttymxc1"
24 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
29 /* Size of malloc() pool */
30 #define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M)
33 #define CONFIG_FEC_MXC
34 #define IMX_FEC_BASE ENET_BASE_ADDR
35 #define CONFIG_FEC_XCV_TYPE RGMII
36 #define CONFIG_ETHPRIME "FEC"
37 #define CONFIG_FEC_MXC_PHYADDR 3
42 #define CONFIG_SYS_I2C
43 #define CONFIG_SYS_I2C_MXC
44 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 2 */
45 #define CONFIG_SYS_I2C_SPEED 100000
47 #ifndef CONFIG_SPL_BUILD
48 /* Enable NAND support */
49 #define CONFIG_SYS_MAX_NAND_DEVICE 1
50 #define CONFIG_SYS_NAND_BASE 0x40000000
51 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
52 #define CONFIG_SYS_NAND_ONFI_DETECTION
55 /* DMA stuff, needed for GPMI/MXS NAND support */
57 /* Filesystem support */
59 /* Physical Memory Map */
60 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
62 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
63 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
64 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
66 #define CONFIG_SYS_INIT_SP_OFFSET \
67 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
68 #define CONFIG_SYS_INIT_SP_ADDR \
69 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
72 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
73 #define CONFIG_SYS_FSL_USDHC_NUM 1
75 /* Environment organization */