2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * Configuration settings for the phytec PCM-052 SoM.
6 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/imx-regs.h>
16 #define CONFIG_DISPLAY_CPUINFO
17 #define CONFIG_DISPLAY_BOARDINFO
18 #define CONFIG_SYS_THUMB_BUILD
20 #define CONFIG_SKIP_LOWLEVEL_INIT
22 /* Enable passing of ATAGs */
23 #define CONFIG_CMDLINE_TAG
25 /* Size of malloc() pool */
26 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
28 #define CONFIG_BOARD_EARLY_INIT_F
30 /* Allow to overwrite serial and ethaddr */
31 #define CONFIG_ENV_OVERWRITE
32 #define CONFIG_BAUDRATE 115200
35 #define CONFIG_CMD_NAND
36 #define CONFIG_CMD_NAND_TRIMFFS
37 #define CONFIG_SYS_NAND_ONFI_DETECTION
39 #ifdef CONFIG_CMD_NAND
40 #define CONFIG_USE_ARCH_MEMCPY
41 #define CONFIG_SYS_MAX_NAND_DEVICE 1
42 #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
44 #define CONFIG_JFFS2_NAND
47 #define CONFIG_CMD_UBI
48 #define CONFIG_CMD_UBIFS
52 /* Dynamic MTD partition support */
53 #define CONFIG_CMD_MTDPARTS
54 #define CONFIG_MTD_PARTITIONS
55 #define CONFIG_MTD_DEVICE
56 #define MTDIDS_DEFAULT "nand0=NAND"
57 #define MTDPARTS_DEFAULT "mtdparts=NAND:256k(spare)"\
68 #define CONFIG_FSL_ESDHC
69 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
70 #define CONFIG_SYS_FSL_ESDHC_NUM 1
72 /*#define CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ1*/
73 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135
74 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
75 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
77 #define CONFIG_GENERIC_MMC
78 #define CONFIG_DOS_PARTITION
80 #define CONFIG_FEC_MXC
82 #define IMX_FEC_BASE ENET_BASE_ADDR
83 #define CONFIG_FEC_XCV_TYPE RMII
84 #define CONFIG_FEC_MXC_PHYADDR 0
86 #define CONFIG_PHY_MICREL
90 #ifdef CONFIG_FSL_QSPI
91 #define CONFIG_SPI_FLASH
92 #define FSL_QSPI_FLASH_SIZE (1 << 24)
93 #define FSL_QSPI_FLASH_NUM 2
94 #define CONFIG_SYS_FSL_QSPI_LE
98 #define CONFIG_SYS_I2C
99 #define CONFIG_SYS_I2C_MXC_I2C3
100 #define CONFIG_SYS_I2C_MXC
102 /* RTC (actually an RV-4162 but M41T62-compatible) */
103 #define CONFIG_CMD_DATE
104 #define CONFIG_RTC_M41T62
105 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
106 #define CONFIG_SYS_RTC_BUS_NUM 2
108 /* EEPROM (24FC256) */
109 #define CONFIG_CMD_EEPROM
110 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
111 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
112 #define CONFIG_SYS_I2C_EEPROM_BUS 2
115 #define CONFIG_LOADADDR 0x82000000
117 /* We boot from the gfxRAM area of the OCRAM. */
118 #define CONFIG_SYS_TEXT_BASE 0x3f408000
119 #define CONFIG_BOARD_SIZE_LIMIT 524288
121 #define CONFIG_BOOTCOMMAND "run bootcmd_sd"
122 #define CONFIG_EXTRA_ENV_SETTINGS \
123 "fdt_high=0xffffffff\0" \
124 "initrd_high=0xffffffff\0" \
125 "blimg_file=u-boot.imx\0" \
126 "blsec_addr=0x81000000\0" \
127 "blimg_addr=0x81000400\0" \
128 "kernel_file=zImage\0" \
129 "kernel_addr=0x82000000\0" \
130 "fdt_file=vf610-pcm052.dtb\0" \
131 "fdt_addr=0x81000000\0" \
132 "ram_file=uRamdisk\0" \
133 "ram_addr=0x83000000\0" \
134 "filesys=rootfs.ubifs\0" \
135 "sys_addr=0x81000000\0" \
136 "tftploc=/path/to/tftp/directory/\0" \
137 "nfs_root=/path/to/nfs/root\0" \
138 "tftptimeout=1000\0" \
139 "tftptimeoutcountmax=1000000\0" \
140 "mtdparts=" MTDPARTS_DEFAULT "\0" \
141 "bootargs_base=setenv bootargs rw mem=256M " \
142 "console=ttyLP1,115200n8\0" \
143 "bootargs_sd=setenv bootargs ${bootargs} " \
144 "root=/dev/mmcblk0p2 rootwait\0" \
145 "bootargs_net=setenv bootargs ${bootargs} root=/dev/nfs ip=dhcp " \
146 "nfsroot=${serverip}:${nfs_root},v3,tcp\0" \
147 "bootargs_nand=setenv bootargs ${bootargs} " \
148 "ubi.mtd=6 rootfstype=ubifs root=ubi0:rootfs\0" \
149 "bootargs_ram=setenv bootargs ${bootargs} " \
150 "root=/dev/ram rw initrd=${ram_addr}\0" \
151 "bootargs_mtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
152 "bootcmd_sd=run bootargs_base bootargs_sd bootargs_mtd; " \
153 "fatload mmc 0:1 ${kernel_addr} ${kernel_file}; " \
154 "fatload mmc 0:1 ${fdt_addr} ${fdt_file}; " \
155 "bootz ${kernel_addr} - ${fdt_addr}\0" \
156 "bootcmd_net=run bootargs_base bootargs_net bootargs_mtd; " \
157 "tftpboot ${kernel_addr} ${tftpdir}${kernel_file}; " \
158 "tftpboot ${fdt_addr} ${tftpdir}${fdt_file}; " \
159 "bootz ${kernel_addr} - ${fdt_addr}\0" \
160 "bootcmd_nand=run bootargs_base bootargs_nand bootargs_mtd; " \
161 "nand read ${fdt_addr} dtb; " \
162 "nand read ${kernel_addr} kernel; " \
163 "bootz ${kernel_addr} - ${fdt_addr}\0" \
164 "bootcmd_ram=run bootargs_base bootargs_ram bootargs_mtd; " \
165 "nand read ${fdt_addr} dtb; " \
166 "nand read ${kernel_addr} kernel; " \
167 "nand read ${ram_addr} ramdisk; " \
168 "bootz ${kernel_addr} ${ram_addr} ${fdt_addr}\0" \
169 "update_bootloader_from_tftp=mtdparts default; " \
170 "nand read ${blsec_addr} bootloader; " \
171 "mw.b ${blimg_addr} 0xff 0x5FC00; " \
172 "if tftp ${blimg_addr} ${tftpdir}${blimg_file}; then " \
173 "nand erase.part bootloader; " \
174 "nand write ${blsec_addr} bootloader ${filesize}; fi\0" \
175 "update_kernel_from_sd=if fatload mmc 0:2 ${kernel_addr} " \
177 "then mtdparts default; " \
178 "nand erase.part kernel; " \
179 "nand write ${kernel_addr} kernel ${filesize}; " \
180 "if fatload mmc 0:2 ${fdt_addr} ${fdt_file}; then " \
181 "nand erase.part dtb; " \
182 "nand write ${fdt_addr} dtb ${filesize}; fi\0" \
183 "update_kernel_from_tftp=if tftp ${fdt_addr} ${tftpdir}${fdt_file}; " \
184 "then setenv fdtsize ${filesize}; " \
185 "if tftp ${kernel_addr} ${tftpdir}${kernel_file}; then " \
186 "mtdparts default; " \
187 "nand erase.part dtb; " \
188 "nand write ${fdt_addr} dtb ${fdtsize}; " \
189 "nand erase.part kernel; " \
190 "nand write ${kernel_addr} kernel ${filesize}; fi; fi\0" \
191 "update_rootfs_from_tftp=if tftp ${sys_addr} ${tftpdir}${filesys}; " \
192 "then mtdparts default; " \
193 "nand erase.part root; " \
195 "ubi create rootfs; " \
196 "ubi write ${sys_addr} rootfs ${filesize}; fi\0" \
197 "update_ramdisk_from_tftp=if tftp ${ram_addr} ${tftpdir}${ram_file}; " \
198 "then mtdparts default; " \
199 "nand erase.part ramdisk; " \
200 "nand write ${ram_addr} ramdisk ${filesize}; fi\0"
202 /* Miscellaneous configurable options */
203 #define CONFIG_SYS_LONGHELP /* undef to save memory */
204 #define CONFIG_AUTO_COMPLETE
205 #define CONFIG_CMDLINE_EDITING
206 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
207 #define CONFIG_SYS_PBSIZE \
208 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
209 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
210 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
212 #define CONFIG_SYS_MEMTEST_START 0x80010000
213 #define CONFIG_SYS_MEMTEST_END 0x87C00000
215 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
219 * The stack sizes are set up in start.S using the settings below
221 #define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
223 /* Physical memory map */
224 #define CONFIG_NR_DRAM_BANKS 1
225 #define PHYS_SDRAM (0x80000000)
226 #define PHYS_SDRAM_SIZE (256 * 1024 * 1024)
228 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
229 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
230 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
232 #define CONFIG_SYS_INIT_SP_OFFSET \
233 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
234 #define CONFIG_SYS_INIT_SP_ADDR \
235 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
237 /* FLASH and environment organization */
238 #define CONFIG_SYS_NO_FLASH
240 #ifdef CONFIG_ENV_IS_IN_MMC
241 #define CONFIG_ENV_SIZE (8 * 1024)
243 #define CONFIG_ENV_OFFSET (12 * 64 * 1024)
244 #define CONFIG_SYS_MMC_ENV_DEV 0
247 #ifdef CONFIG_ENV_IS_IN_NAND
248 #define CONFIG_ENV_SECT_SIZE (128 * 1024)
249 #define CONFIG_ENV_SIZE (8 * 1024)
250 #define CONFIG_ENV_OFFSET 0xA0000
251 #define CONFIG_ENV_SIZE_REDUND (8 * 1024)
252 #define CONFIG_ENV_OFFSET_REDUND 0xC0000