1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Board configuration file for Phytec phyBOARD-i.MX6ULL-Segin SBC
4 * Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com>
6 * Based on include/configs/xpress.h:
7 * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
10 #define __PCL063_ULL_H
12 #include <linux/sizes.h>
13 #include <linux/stringify.h>
14 #include "mx6_common.h"
16 #define CFG_SYS_FSL_USDHC_NUM 2
18 /* Environment settings */
20 /* Environment in SD */
21 #define MMC_ROOTFS_DEV 0
22 #define MMC_ROOTFS_PART 2
25 #define CONFIG_MXC_UART_BASE UART1_BASE
29 #define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
33 /* Miscellaneous configurable options */
35 /* Physical Memory Map */
36 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
37 #define PHYS_SDRAM_SIZE SZ_256M
39 #define CFG_SYS_SDRAM_BASE PHYS_SDRAM
40 #define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
41 #define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
44 #define CFG_SYS_NAND_BASE 0x40000000
47 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
48 #define CONFIG_MXC_USB_FLAGS 0
51 "mmcdev=" __stringify(MMC_ROOTFS_DEV) "\0" \
52 "mmcpart=" __stringify(MMC_ROOTFS_PART) "\0" \
56 "optargs=rw rootwait\0" \
57 "mmcautodetect=yes\0" \
58 "mmcrootfstype=ext4\0" \
59 "mmcfit_name=fitImage\0" \
60 "mmcloadfit=fatload mmc ${mmcdev}:${fitpart} ${fit_addr} " \
62 "mmcargs=setenv bootargs " \
63 "root=/dev/mmcblk${mmcdev}p${mmcpart} ${optargs} " \
64 "console=${console} rootfstype=${mmcrootfstype}\0" \
65 "mmc_mmc_fit=run mmcloadfit;run mmcargs addcon; bootm ${fit_addr}\0" \
67 /* Default environment */
68 #define CFG_EXTRA_ENV_SETTINGS \
69 "fdt_high=0xffffffff\0" \
70 "console=ttymxc0,115200n8\0" \
71 "addcon=setenv bootargs ${bootargs} console=${console},${baudrate}\0" \
72 "fit_addr=0x82000000\0" \
75 #define BOOT_TARGET_DEVICES(func) \
80 #include <config_distro_bootcmd.h>
82 #endif /* __PCL063_ULL_H */