1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2018 Collabora Ltd.
5 * Based on include/configs/xpress.h:
6 * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
11 #include <linux/sizes.h>
12 #include "mx6_common.h"
18 * There is a bug in some i.MX6UL processors that results in the initial
19 * portion of OCRAM being unavailable when booting from (at least) an SD
22 * Tweak the SPL text base address to avoid this.
25 #define CONFIG_SYS_FSL_USDHC_NUM 1
27 /* Size of malloc() pool */
28 #define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
31 #define CONFIG_MXC_UART_BASE UART1_BASE
35 #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
37 /* Miscellaneous configurable options */
39 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
40 #define CONFIG_SYS_HZ 1000
42 /* Physical Memory Map */
43 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
44 #define PHYS_SDRAM_SIZE SZ_256M
46 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
47 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
48 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
50 #define CONFIG_SYS_INIT_SP_OFFSET \
51 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
52 #define CONFIG_SYS_INIT_SP_ADDR \
53 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
56 #define CONFIG_SYS_MAX_NAND_DEVICE 1
57 #define CONFIG_SYS_NAND_BASE 0x40000000
60 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
61 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
62 #define CONFIG_MXC_USB_FLAGS 0
63 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
65 #define CONFIG_EXTRA_ENV_SETTINGS \
66 "console=ttymxc0,115200n8\0" \
67 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
68 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
69 "fdt_addr_r=0x82000000\0" \
70 "fdt_high=0xffffffff\0" \
71 "initrd_high=0xffffffff\0" \
72 "kernel_addr_r=0x81000000\0" \
73 "pxefile_addr_r=0x87100000\0" \
74 "ramdisk_addr_r=0x82100000\0" \
75 "scriptaddr=0x87000000\0" \
78 #define BOOT_TARGET_DEVICES(func) \
80 func(UBIFS, ubifs, 0) \
84 #include <config_distro_bootcmd.h>
86 #endif /* __PCL063_H */