3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 * This file contains the configuration parameters for the dbau1x00 board.
15 #define CONFIG_PB1X00 1
16 #define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
19 #define CONFIG_SOC_AU1000 1
22 #define CONFIG_SOC_AU1100 1
25 #define CONFIG_SOC_AU1500 1
27 #error "No valid board set"
32 #define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */
34 #define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
36 #define CONFIG_BAUDRATE 115200
38 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
39 #undef CONFIG_BOOTARGS
41 #define CONFIG_EXTRA_ENV_SETTINGS \
42 "addmisc=setenv bootargs ${bootargs} " \
43 "console=ttyS0,${baudrate} " \
45 "bootfile=/vmlinux.img\0" \
46 "load=tftp 80500000 ${u-boot}\0" \
48 /* Boot from NFS root */
49 #define CONFIG_BOOTCOMMAND "bootp; setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; bootm"
52 * Miscellaneous configurable options
54 #define CONFIG_SYS_LONGHELP /* undef to save memory */
55 #define CONFIG_SYS_PROMPT "Pb1x00 # " /* Monitor Command Prompt */
56 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
57 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
58 #define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
60 #define CONFIG_SYS_MALLOC_LEN 128*1024
62 #define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
64 #define CONFIG_SYS_MIPS_TIMER_FREQ 396000000
66 #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
68 #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */
70 #define CONFIG_SYS_MEMTEST_START 0x80100000
71 #undef CONFIG_SYS_MEMTEST_START
72 #define CONFIG_SYS_MEMTEST_START 0x80200000
73 #define CONFIG_SYS_MEMTEST_END 0x83800000
75 /*-----------------------------------------------------------------------
76 * FLASH and environment organization
78 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
79 #define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
81 #define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */
82 #define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */
84 /* The following #defines are needed to get flash environment right */
85 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
86 #define CONFIG_SYS_MONITOR_LEN (192 << 10)
88 #define CONFIG_SYS_INIT_SP_OFFSET 0x4000000
90 /* We boot from this flash, selected with dip switch */
91 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2
93 /* timeout values are in ticks */
94 #define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
95 #define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
97 #define CONFIG_ENV_IS_NOWHERE 1
99 /* Address and size of Primary Environment Sector */
100 #define CONFIG_ENV_ADDR 0xB0030000
101 #define CONFIG_ENV_SIZE 0x10000
103 #define CONFIG_FLASH_16BIT
105 #define CONFIG_NR_DRAM_BANKS 2
108 #define CONFIG_MEMSIZE_IN_BYTES
111 /*---USB -------------------------------------------*/
113 #define CONFIG_USB_OHCI
114 #define CONFIG_USB_STORAGE
115 #define CONFIG_DOS_PARTITION
118 /*---ATA PCMCIA ------------------------------------*/
120 #define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
121 #define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000
122 #define CONFIG_PCMCIA_SLOT_A
124 #define CONFIG_ATAPI 1
125 #define CONFIG_MAC_PARTITION 1
127 /* We run CF in "true ide" mode or a harddrive via pcmcia */
128 #define CONFIG_IDE_PCMCIA 1
130 /* We only support one slot for now */
131 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
132 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
134 #undef CONFIG_IDE_LED /* LED for ide not supported */
135 #undef CONFIG_IDE_RESET /* reset for ide not supported */
137 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
139 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
141 /* Offset for data I/O */
142 #define CONFIG_SYS_ATA_DATA_OFFSET 8
144 /* Offset for normal register accesses */
145 #define CONFIG_SYS_ATA_REG_OFFSET 0
147 /* Offset for alternate registers */
148 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
151 /*-----------------------------------------------------------------------
152 * Cache Configuration
154 #define CONFIG_SYS_DCACHE_SIZE 16384
155 #define CONFIG_SYS_ICACHE_SIZE 16384
156 #define CONFIG_SYS_CACHELINE_SIZE 32
162 #define CONFIG_BOOTP_BOOTFILESIZE
163 #define CONFIG_BOOTP_BOOTPATH
164 #define CONFIG_BOOTP_GATEWAY
165 #define CONFIG_BOOTP_HOSTNAME
169 * Command line configuration.
171 #include <config_cmd_default.h>
173 #define CONFIG_CMD_DHCP
174 #define CONFIG_CMD_ELF
175 #define CONFIG_CMD_MII
176 #define CONFIG_CMD_PING
178 #undef CONFIG_CMD_SAVEENV
179 #undef CONFIG_CMD_FAT
180 #undef CONFIG_CMD_FLASH
181 #undef CONFIG_CMD_FPGA
182 #undef CONFIG_CMD_IDE
183 #undef CONFIG_CMD_LOADS
184 #undef CONFIG_CMD_RUN
185 #undef CONFIG_CMD_LOADB
186 #undef CONFIG_CMD_ELF
187 #undef CONFIG_CMD_BDI
188 #undef CONFIG_CMD_BEDBUG
190 #endif /* __CONFIG_H */