2 * Palm Tungsten|C configuration file
4 * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
6 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/pxa-regs.h>
15 * High Level Board Configuration Options
17 #define CONFIG_CPU_PXA25X 1 /* Intel PXA255 CPU */
18 #define CONFIG_PALMTC 1 /* Palm Tungsten|C board */
20 /* we will never enable dcache, because we have to setup MMU first */
21 #define CONFIG_SYS_DCACHE_OFF
24 * Environment settings
26 #define CONFIG_ENV_OVERWRITE
27 #define CONFIG_SYS_MALLOC_LEN (128*1024)
28 #define CONFIG_SYS_TEXT_BASE 0x0
30 #define CONFIG_BOOTCOMMAND \
31 "if mmc init && fatload mmc 0 0xa0000000 uboot.script ; then " \
32 "source 0xa0000000; " \
36 #define CONFIG_BOOTARGS \
37 "console=tty0 console=ttyS0,115200"
38 #define CONFIG_TIMESTAMP
39 #define CONFIG_BOOTDELAY 2 /* Autoboot delay */
40 #define CONFIG_CMDLINE_TAG
41 #define CONFIG_SETUP_MEMORY_TAGS
43 #define CONFIG_LZMA /* LZMA compression support */
46 * Serial Console Configuration
47 * STUART - the lower serial port on Colibri board
49 #define CONFIG_PXA_SERIAL
50 #define CONFIG_FFUART 1
51 #define CONFIG_CONS_INDEX 3
52 #define CONFIG_BAUDRATE 115200
55 * Bootloader Components Configuration
57 #include <config_cmd_default.h>
61 #define CONFIG_CMD_ENV
62 #define CONFIG_CMD_MMC
64 #define CONFIG_PXA_LCD
67 * MMC Card Configuration
71 #define CONFIG_GENERIC_MMC
72 #define CONFIG_PXA_MMC_GENERIC
73 #define CONFIG_SYS_MMC_BASE 0xF0000000
74 #define CONFIG_CMD_FAT
75 #define CONFIG_CMD_EXT2
76 #define CONFIG_DOS_PARTITION
83 #define CONFIG_ACX517AKN
84 #define CONFIG_VIDEO_LOGO
85 #define CONFIG_CMD_BMP
86 #define CONFIG_SPLASH_SCREEN
87 #define CONFIG_SPLASH_SCREEN_ALIGN
88 #define CONFIG_VIDEO_BMP_GZIP
89 #define CONFIG_VIDEO_BMP_RLE8
90 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
96 #ifdef CONFIG_CMD_KGDB
97 #define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */
101 * HUSH Shell Configuration
103 #define CONFIG_SYS_HUSH_PARSER 1
105 #define CONFIG_SYS_LONGHELP
106 #ifdef CONFIG_SYS_HUSH_PARSER
107 #define CONFIG_SYS_PROMPT "$ "
109 #define CONFIG_SYS_CBSIZE 256
110 #define CONFIG_SYS_PBSIZE \
111 (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
112 #define CONFIG_SYS_MAXARGS 16
113 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
114 #define CONFIG_SYS_DEVICE_NULLDEV 1
117 * Clock Configuration
119 #undef CONFIG_SYS_CLKS_IN_HZ
120 #define CONFIG_SYS_CPUSPEED 0x161 /* 400MHz;L=1 M=3 T=1 */
125 #define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
126 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
127 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
129 #define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
130 #define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */
132 #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
133 #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
135 #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE
137 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
138 #define CONFIG_SYS_INIT_SP_ADDR 0xfffff800
143 #ifdef CONFIG_CMD_FLASH
144 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
145 #define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */
146 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
148 #define CONFIG_SYS_FLASH_CFI
149 #define CONFIG_FLASH_CFI_DRIVER 1
150 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
152 #define CONFIG_SYS_MAX_FLASH_BANKS 1
153 #define CONFIG_SYS_MAX_FLASH_SECT 64
155 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
157 #define CONFIG_SYS_FLASH_ERASE_TOUT 240000
158 #define CONFIG_SYS_FLASH_WRITE_TOUT 240000
159 #define CONFIG_SYS_FLASH_LOCK_TOUT 240000
160 #define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000
161 #define CONFIG_SYS_FLASH_PROTECTION
163 #define CONFIG_ENV_IS_IN_FLASH 1
164 #define CONFIG_ENV_SECT_SIZE 0x40000
166 #define CONFIG_SYS_NO_FLASH
167 #define CONFIG_ENV_IS_NOWHERE
170 #define CONFIG_SYS_MONITOR_BASE 0x0
171 #define CONFIG_SYS_MONITOR_LEN 0x40000
173 #define CONFIG_ENV_SIZE 0x4000
174 #define CONFIG_ENV_ADDR 0x40000
179 #define CONFIG_SYS_GAFR0_L_VAL 0x00011004
180 #define CONFIG_SYS_GAFR0_U_VAL 0xa5000008
181 #define CONFIG_SYS_GAFR1_L_VAL 0x60888050
182 #define CONFIG_SYS_GAFR1_U_VAL 0xaaa50aaa
183 #define CONFIG_SYS_GAFR2_L_VAL 0x0aaaaaaa
184 #define CONFIG_SYS_GAFR2_U_VAL 0x00000000
185 #define CONFIG_SYS_GPCR0_VAL 0x0
186 #define CONFIG_SYS_GPCR1_VAL 0x0
187 #define CONFIG_SYS_GPCR2_VAL 0x0
188 #define CONFIG_SYS_GPDR0_VAL 0xcfff8140
189 #define CONFIG_SYS_GPDR1_VAL 0xfcbfbef3
190 #define CONFIG_SYS_GPDR2_VAL 0x0001ffff
191 #define CONFIG_SYS_GPSR0_VAL 0x00010f8f
192 #define CONFIG_SYS_GPSR1_VAL 0x00bf5de5
193 #define CONFIG_SYS_GPSR2_VAL 0x03fe0800
195 #define CONFIG_SYS_PSSR_VAL PSSR_RDH
198 * CKEN[1] - PWM1 ; CKEN[6] - FFUART
199 * CKEN[12] - MMC ; CKEN[16] - LCD
201 #define CONFIG_SYS_CKEN 0x00011042
202 #define CONFIG_SYS_CCCR 0x00000161
207 #define CONFIG_SYS_MSC0_VAL 0x800092c2
208 #define CONFIG_SYS_MSC1_VAL 0x80008000
209 #define CONFIG_SYS_MSC2_VAL 0x80008000
210 #define CONFIG_SYS_MDCNFG_VAL 0x00001ac9
211 #define CONFIG_SYS_MDREFR_VAL 0x00118018
212 #define CONFIG_SYS_MDMRS_VAL 0x00220032
213 #define CONFIG_SYS_FLYCNFG_VAL 0x01fe01fe
214 #define CONFIG_SYS_SXCNFG_VAL 0x00000000
217 * PCMCIA and CF Interfaces
219 #define CONFIG_SYS_MECR_VAL 0x00000000
220 #define CONFIG_SYS_MCMEM0_VAL 0x00010504
221 #define CONFIG_SYS_MCMEM1_VAL 0x00010504
222 #define CONFIG_SYS_MCATT0_VAL 0x00010504
223 #define CONFIG_SYS_MCATT1_VAL 0x00010504
224 #define CONFIG_SYS_MCIO0_VAL 0x00010e04
225 #define CONFIG_SYS_MCIO1_VAL 0x00010e04
227 #endif /* __CONFIG_H */