powerpc:Rename CONFIG_PBLRCW_CONFIG & CONFIG_SYS_FSL_PBL_PBI
[platform/kernel/u-boot.git] / include / configs / palmld.h
1 /*
2  * Palm LifeDrive configuration file
3  *
4  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
5  *
6  * SPDX-License-Identifier:     GPL-2.0+
7  */
8
9 #ifndef __CONFIG_H
10 #define __CONFIG_H
11
12 /*
13  * High Level Board Configuration Options
14  */
15 #define CONFIG_CPU_PXA27X               1       /* Marvell PXA270 CPU */
16 #define CONFIG_PALMLD           1       /* Palm LifeDrive board */
17
18 /* we will never enable dcache, because we have to setup MMU first */
19 #define CONFIG_SYS_DCACHE_OFF
20
21 /*
22  * Environment settings
23  */
24 #define CONFIG_ENV_OVERWRITE
25 #define CONFIG_SYS_MALLOC_LEN           (128*1024)
26 #define CONFIG_SYS_TEXT_BASE    0x0
27
28 #define CONFIG_BOOTCOMMAND                                              \
29         "if mmcinfo && fatload mmc 0 0xa0000000 uboot.script ; then "   \
30                 "source 0xa0000000; "                                   \
31         "else "                                                         \
32                 "bootm 0x0x60000; "                                     \
33         "fi; "
34 #define CONFIG_BOOTARGS                 "console=tty0 console=ttyS0,9600"
35 #define CONFIG_TIMESTAMP
36 #define CONFIG_BOOTDELAY                2       /* Autoboot delay */
37 #define CONFIG_CMDLINE_TAG
38 #define CONFIG_SETUP_MEMORY_TAGS
39
40 #define CONFIG_LZMA                     /* LZMA compression support */
41
42 /*
43  * Serial Console Configuration
44  */
45 #define CONFIG_PXA_SERIAL
46 #define CONFIG_FFUART                   1
47 #define CONFIG_CONS_INDEX               3
48 #define CONFIG_BAUDRATE                 9600
49
50 /*
51  * Bootloader Components Configuration
52  */
53 #include <config_cmd_default.h>
54
55 #undef  CONFIG_CMD_NET
56 #undef  CONFIG_CMD_NFS
57 #define CONFIG_CMD_ENV
58 #undef  CONFIG_CMD_IMLS
59 #define CONFIG_CMD_MMC
60 #define CONFIG_CMD_IDE
61 #define CONFIG_LCD
62 #define CONFIG_PXA_LCD
63
64 /*
65  * MMC Card Configuration
66  */
67 #ifdef  CONFIG_CMD_MMC
68 #define CONFIG_MMC
69 #define CONFIG_GENERIC_MMC
70 #define CONFIG_PXA_MMC_GENERIC
71 #define CONFIG_SYS_MMC_BASE             0xF0000000
72 #define CONFIG_CMD_FAT
73 #define CONFIG_CMD_EXT2
74 #define CONFIG_DOS_PARTITION
75 #endif
76
77 /*
78  * LCD
79  */
80 #ifdef CONFIG_LCD
81 #define CONFIG_LQ038J7DH53
82 #define CONFIG_VIDEO_LOGO
83 #define CONFIG_CMD_BMP
84 #define CONFIG_SPLASH_SCREEN
85 #define CONFIG_SPLASH_SCREEN_ALIGN
86 #define CONFIG_VIDEO_BMP_GZIP
87 #define CONFIG_VIDEO_BMP_RLE8
88 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE  (2 << 20)
89 #endif
90
91 /*
92  * KGDB
93  */
94 #ifdef  CONFIG_CMD_KGDB
95 #define CONFIG_KGDB_BAUDRATE            230400  /* kgdb serial port speed */
96 #endif
97
98 /*
99  * HUSH Shell Configuration
100  */
101 #define CONFIG_SYS_HUSH_PARSER          1
102
103 #define CONFIG_SYS_LONGHELP
104 #ifdef  CONFIG_SYS_HUSH_PARSER
105 #define CONFIG_SYS_PROMPT               "$ "
106 #endif
107 #define CONFIG_SYS_CBSIZE               256
108 #define CONFIG_SYS_PBSIZE               \
109         (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
110 #define CONFIG_SYS_MAXARGS              16
111 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
112 #define CONFIG_SYS_DEVICE_NULLDEV       1
113
114 /*
115  * Clock Configuration
116  */
117 #undef  CONFIG_SYS_CLKS_IN_HZ
118 #define CONFIG_SYS_HZ                   1000
119 #define CONFIG_SYS_CPUSPEED             0x210           /* 416MHz ; N=2,L=16 */
120
121 /*
122  * DRAM Map
123  */
124 #define CONFIG_NR_DRAM_BANKS            1               /* 1 bank of DRAM */
125 #define PHYS_SDRAM_1                    0xa0000000      /* SDRAM Bank #1 */
126 #define PHYS_SDRAM_1_SIZE               0x02000000      /* 32 MB */
127
128 #define CONFIG_SYS_DRAM_BASE            0xa0000000      /* CS0 */
129 #define CONFIG_SYS_DRAM_SIZE            0x02000000      /* 32 MB DRAM */
130
131 #define CONFIG_SYS_MEMTEST_START        0xa0400000      /* memtest works on */
132 #define CONFIG_SYS_MEMTEST_END          0xa0800000      /* 4 ... 8 MB in DRAM */
133
134 #define CONFIG_SYS_LOAD_ADDR            CONFIG_SYS_DRAM_BASE
135
136 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
137 #define CONFIG_SYS_INIT_SP_ADDR         (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
138
139 /*
140  * NOR FLASH
141  */
142 #ifdef  CONFIG_CMD_FLASH
143 #define PHYS_FLASH_1                    0x00000000      /* Flash Bank #1 */
144 #define PHYS_FLASH_SIZE                 0x00080000      /* 512 KB */
145 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
146
147 #define CONFIG_SYS_FLASH_CFI
148 #define CONFIG_FLASH_CFI_DRIVER         1
149
150 #define CONFIG_FLASH_CFI_LEGACY
151 #define CONFIG_SYS_FLASH_LEGACY_512Kx16
152
153 #define CONFIG_SYS_MONITOR_BASE         0
154 #define CONFIG_SYS_MONITOR_LEN          0x40000
155
156 #define CONFIG_SYS_MAX_FLASH_BANKS      1
157 #define CONFIG_SYS_MAX_FLASH_SECT       256
158
159 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
160
161 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000
162 #define CONFIG_SYS_FLASH_WRITE_TOUT     240000
163 #define CONFIG_SYS_FLASH_LOCK_TOUT      240000
164 #define CONFIG_SYS_FLASH_UNLOCK_TOUT    240000
165 #define CONFIG_SYS_FLASH_PROTECTION
166
167 #define CONFIG_ENV_IS_IN_FLASH          1
168 #define CONFIG_ENV_SECT_SIZE            0x10000
169 #else
170 #define CONFIG_SYS_NO_FLASH
171 #define CONFIG_ENV_IS_NOWHERE
172 #endif
173
174 #define CONFIG_ENV_ADDR                 0x40000
175 #define CONFIG_ENV_SIZE                 0x4000
176
177 /*
178  * IDE
179  */
180 #ifdef  CONFIG_CMD_IDE
181 #define CONFIG_LBA48
182 #undef  CONFIG_IDE_LED
183 #undef  CONFIG_IDE_RESET
184
185 #define __io
186
187 #define CONFIG_SYS_IDE_MAXBUS           1
188 #define CONFIG_SYS_IDE_MAXDEVICE        1
189
190 #define CONFIG_SYS_ATA_BASE_ADDR        0x20000000
191 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0
192
193 #define CONFIG_SYS_ATA_DATA_OFFSET      0x10
194 #define CONFIG_SYS_ATA_REG_OFFSET       0x10
195 #define CONFIG_SYS_ATA_ALT_OFFSET       0x10
196
197 #define CONFIG_SYS_ATA_STRIDE           1
198 #endif
199
200 /*
201  * GPIO settings
202  */
203 #define CONFIG_SYS_GAFR0_L_VAL  0x00000000
204 #define CONFIG_SYS_GAFR0_U_VAL  0xa5180012
205 #define CONFIG_SYS_GAFR1_L_VAL  0x69988056
206 #define CONFIG_SYS_GAFR1_U_VAL  0xaaa580aa
207 #define CONFIG_SYS_GAFR2_L_VAL  0x6aaaaaaa
208 #define CONFIG_SYS_GAFR2_U_VAL  0x01040001
209 #define CONFIG_SYS_GAFR3_L_VAL  0x540a950c
210 #define CONFIG_SYS_GAFR3_U_VAL  0x00000009
211 #define CONFIG_SYS_GPCR0_VAL    0x00000000
212 #define CONFIG_SYS_GPCR1_VAL    0x00000000
213 #define CONFIG_SYS_GPCR2_VAL    0x00000000
214 #define CONFIG_SYS_GPCR3_VAL    0x00000000
215 #define CONFIG_SYS_GPDR0_VAL    0xc26b0000
216 #define CONFIG_SYS_GPDR1_VAL    0xfcdfaa93
217 #define CONFIG_SYS_GPDR2_VAL    0x7bbaffff
218 #define CONFIG_SYS_GPDR3_VAL    0x006ff38d
219 #define CONFIG_SYS_GPSR0_VAL    0x0d9e45ee
220 #define CONFIG_SYS_GPSR1_VAL    0x03affdae
221 #define CONFIG_SYS_GPSR2_VAL    0x07554000
222 #define CONFIG_SYS_GPSR3_VAL    0x01bc0785
223
224 #define CONFIG_SYS_PSSR_VAL     0x30
225
226 /*
227  * Clock settings
228  */
229 #define CONFIG_SYS_CKEN         0x01ffffff
230 #define CONFIG_SYS_CCCR         0x02000210
231
232 /*
233  * Memory settings
234  */
235 #define CONFIG_SYS_MSC0_VAL     0x7ff844c8
236 #define CONFIG_SYS_MSC1_VAL     0x7ff86ab4
237 #define CONFIG_SYS_MSC2_VAL     0x7ff87ff8
238 #define CONFIG_SYS_MDCNFG_VAL   0x0B880acd
239 #define CONFIG_SYS_MDREFR_VAL   0x201fa031
240 #define CONFIG_SYS_MDMRS_VAL    0x00320032
241 #define CONFIG_SYS_FLYCNFG_VAL  0x00000000
242 #define CONFIG_SYS_SXCNFG_VAL   0x40044004
243
244 /*
245  * PCMCIA and CF Interfaces
246  */
247 #define CONFIG_SYS_MECR_VAL     0x00000003
248 #define CONFIG_SYS_MCMEM0_VAL   0x0001c391
249 #define CONFIG_SYS_MCMEM1_VAL   0x0001c391
250 #define CONFIG_SYS_MCATT0_VAL   0x0001c391
251 #define CONFIG_SYS_MCATT1_VAL   0x0001c391
252 #define CONFIG_SYS_MCIO0_VAL    0x00014611
253 #define CONFIG_SYS_MCIO1_VAL    0x0001c391
254
255 #endif  /* __CONFIG_H */