include/configs/p3p440.h

   1 /*
   2  * (C) Copyright 2005-2006
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 /************************************************************************
  11  * board/config_p3p440.h - configuration for Prodrive P3P440
  12  ***********************************************************************/
  13
  14 #ifndef __CONFIG_H
  15 #define __CONFIG_H
  16
  17 /*-----------------------------------------------------------------------
  18  * High Level Configuration Options
  19  *----------------------------------------------------------------------*/
  20 #define CONFIG_P3P440           1           /* Board is P3P440          */
  21 #define CONFIG_440GP            1           /* Specifc GP support       */
  22 #define CONFIG_440              1           /* ... PPC440 family        */
  23 #define CONFIG_BOARD_EARLY_INIT_F 1         /* Call board_early_init_f  */
  24 #define CONFIG_MISC_INIT_R      1           /* Call misc_init_r         */
  25
  26 #define CONFIG_SYS_TEXT_BASE    0xFFFC0000
  27
  28 #define CONFIG_SYS_CLK_FREQ     33333333    /* external freq to pll     */
  29
  30 /*-----------------------------------------------------------------------
  31  * Base addresses -- Note these are effective addresses where the
  32  * actual resources get mapped (not physical addresses)
  33  *----------------------------------------------------------------------*/
  34 #define CONFIG_SYS_SDRAM_BASE       0x00000000      /* _must_ be 0              */
  35 #define CONFIG_SYS_FLASH_BASE       0xff800000      /* start of FLASH           */
  36 #define CONFIG_SYS_MONITOR_BASE    0xfffc0000       /* start of monitor         */
  37 #define CONFIG_SYS_PCI_MEMBASE      0x80000000      /* mapped pci memory        */
  38 #define CONFIG_SYS_ISRAM_BASE       0xc0000000      /* internal SRAM            */
  39 #define CONFIG_SYS_PCI_BASE         0xd0000000      /* internal PCI regs        */
  40
  41 #define CONFIG_SYS_USB_BASE         (CONFIG_SYS_PERIPHERAL_BASE + 0x00000000)
  42
  43 /*-----------------------------------------------------------------------
  44  * Initial RAM & stack pointer (placed in internal SRAM)
  45  *----------------------------------------------------------------------*/
  46 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_ISRAM_BASE  /* Initial RAM address   */
  47 #define CONFIG_SYS_INIT_RAM_SIZE        0x2000      /* Size of used area in RAM */
  48
  49 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  50 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  51
  52 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Mon*/
  53 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserve 128 kB for malloc*/
  54
  55 /*-----------------------------------------------------------------------
  56  * DDR SDRAM
  57  *----------------------------------------------------------------------*/
  58 #define CONFIG_SDRAM_BANK0      1       /* init onboard DDR SDRAM bank 0*/
  59 #define CONFIG_SDRAM_ECC                /* enable ECC support           */
  60 #define CONFIG_SYS_SDRAM_TABLE  { \
  61                 {(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \
  62                 {(64 << 20),  12, 0x00082001}} /* 64MB mode 2, 12x9(4)  */
  63
  64 /*-----------------------------------------------------------------------
  65  * Serial Port
  66  *----------------------------------------------------------------------*/
  67 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
  68 #define CONFIG_SYS_NS16550
  69 #define CONFIG_SYS_NS16550_SERIAL
  70 #define CONFIG_SYS_NS16550_REG_SIZE     1
  71 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
  72
  73 #undef CONFIG_SYS_EXT_SERIAL_CLOCK
  74 #define CONFIG_BAUDRATE         115200
  75
  76 #define CONFIG_SYS_BAUDRATE_TABLE                                               \
  77         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,               \
  78                         57600, 115200, 230400, 460800, 921600 }
  79
  80 /*-----------------------------------------------------------------------
  81  * I2C
  82  *----------------------------------------------------------------------*/
  83 #define CONFIG_SYS_I2C
  84 #define CONFIG_SYS_I2C_PPC4XX
  85 #define CONFIG_SYS_I2C_PPC4XX_CH0
  86 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           100000
  87 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
  88 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }   /* Don't probe these addrs */
  89
  90 /*-----------------------------------------------------------------------
  91  * I2C RTC
  92  *----------------------------------------------------------------------*/
  93 #define CONFIG_RTC_MAX6900      1               /* MAX6900 RTC          */
  94
  95 /*-----------------------------------------------------------------------
  96  * I2C EEPROM (PCF8594C) for environment
  97  *----------------------------------------------------------------------*/
  98 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x54    /* EEPROM PCF8594C              */
  99 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1        /* Bytes of address             */
 100 /* mask of address bits that overflow into the "EEPROM chip address"    */
 101 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 102 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3     /* The Philips PCF8594C has     */
 103                                         /* 8 byte page write mode using */
 104                                         /* last 3 bits of the address   */
 105 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   40   /* and takes up to 40 msec */
 106
 107 /*-----------------------------------------------------------------------
 108  * Default configuration (environment varibles...)
 109  *----------------------------------------------------------------------*/
 110 #define CONFIG_PREBOOT  "echo;" \
 111         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 112         "echo"
 113
 114 #undef  CONFIG_BOOTARGS
 115
 116 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 117         "netdev=eth0\0"                                                 \
 118         "hostname=p3p440\0"                                             \
 119         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 120                 "nfsroot=${serverip}:${rootpath}\0"                     \
 121         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 122         "addip=setenv bootargs ${bootargs} "                            \
 123                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 124                 ":${hostname}:${netdev}:off panic=1\0"                  \
 125         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 126         "flash_nfs=run nfsargs addip addtty;"                           \
 127                 "bootm ${kernel_addr}\0"                                \
 128         "flash_self=run ramargs addip addtty;"                          \
 129                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 130         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 131                 "bootm\0"                                               \
 132         "rootpath=/opt/eldk/ppc_4xx\0"                                  \
 133         "bootfile=/tftpboot/p3p440/uImage\0"                            \
 134         "kernel_addr=ff800000\0"                                        \
 135         "ramdisk_addr=ff810000\0"                                       \
 136         "load=tftp 100000 /tftpboot/p3p440/u-boot.bin\0"                \
 137         "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"   \
 138                 "cp.b 100000 fffc0000 40000;"                           \
 139                 "setenv filesize;saveenv\0"                             \
 140         "upd=run load update\0"                                         \
 141         "unlock=yes\0"                                                  \
 142         ""
 143 #define CONFIG_BOOTCOMMAND      "run net_nfs"
 144
 145 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
 146
 147 #define CONFIG_BAUDRATE         115200
 148
 149 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 150 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 151
 152 #define CONFIG_PPC4xx_EMAC
 153 #define CONFIG_MII              1       /* MII PHY management           */
 154 #define CONFIG_PHY_ADDR         0x1c    /* PHY address                  */
 155 #define CONFIG_HAS_ETH1
 156 #define CONFIG_PHY1_ADDR        0x1d    /* EMAC1 PHY address            */
 157 #define CONFIG_SYS_RX_ETH_BUFFER        32      /* Number of ethernet rx buffers & descriptors */
 158
 159 #define CONFIG_NETCONSOLE               /* include NetConsole support   */
 160
 161
 162 /*
 163  * BOOTP options
 164  */
 165 #define CONFIG_BOOTP_BOOTFILESIZE
 166 #define CONFIG_BOOTP_BOOTPATH
 167 #define CONFIG_BOOTP_GATEWAY
 168 #define CONFIG_BOOTP_HOSTNAME
 169
 170
 171 /*
 172  * Command line configuration.
 173  */
 174 #include <config_cmd_default.h>
 175
 176 #define CONFIG_CMD_ASKENV
 177 #define CONFIG_CMD_DATE
 178 #define CONFIG_CMD_DHCP
 179 #define CONFIG_CMD_DIAG
 180 #define CONFIG_CMD_ELF
 181 #define CONFIG_CMD_I2C
 182 #define CONFIG_CMD_IRQ
 183 #define CONFIG_CMD_MII
 184 #define CONFIG_CMD_NET
 185 #define CONFIG_CMD_NFS
 186 #define CONFIG_CMD_PCI
 187 #define CONFIG_CMD_PING
 188 #define CONFIG_CMD_REGINFO
 189 #define CONFIG_CMD_EEPROM
 190 #define CONFIG_CMD_SNTP
 191
 192
 193 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 194
 195 /*-----------------------------------------------------------------------
 196  * Miscellaneous configurable options
 197  *----------------------------------------------------------------------*/
 198 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 199 #if defined(CONFIG_CMD_KGDB)
 200 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 201 #else
 202 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 203 #endif
 204 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 205 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 206 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 207
 208 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 209 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 210
 211 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 212 #define CONFIG_SYS_EXTBDINFO            1       /* To use extended board_into (bd_t) */
 213
 214 #define CONFIG_AUTO_COMPLETE    1       /* add autocompletion support   */
 215 #define CONFIG_LOOPW            1       /* enable loopw command         */
 216 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 217 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 218
 219 /*-----------------------------------------------------------------------
 220  * PCI stuff
 221  *----------------------------------------------------------------------*/
 222 /* General PCI */
 223 #define CONFIG_PCI                                  /* include pci support              */
 224 #define CONFIG_PCI_INDIRECT_BRIDGE 1    /* indirect PCI bridge support */
 225 #define CONFIG_PCI_PNP                          /* do pci plug-and-play         */
 226 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 227 #define CONFIG_SYS_PCI_TARGBASE    0x80000000  /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
 228
 229 /* Board-specific PCI */
 230 #define CONFIG_SYS_PCI_TARGET_INIT                  /* let board init pci target    */
 231
 232 #define CONFIG_DISABLE_PISE_TEST        /* disable PISE test (PCIX only)*/
 233
 234 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8   /* AMCC */
 235 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe  /* Whatever */
 236
 237 /*-----------------------------------------------------------------------
 238  * External Bus Controller (EBC) Setup
 239  *----------------------------------------------------------------------*/
 240 #define CONFIG_SYS_FLASH0               0xFF800000
 241 #define CONFIG_SYS_FLASH1               0xFF000000
 242 #define CONFIG_SYS_FLASH2               0xFE800000
 243 #define CONFIG_SYS_FLASH3               0xFE000000
 244 #define CONFIG_SYS_USB                  0xF0000000
 245
 246 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization                       */
 247 #define CONFIG_SYS_EBC_PB0AP            0x03050200
 248 #define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_FLASH0 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
 249
 250 /* Memory Bank 1 (Flash Bank 1, NOR-FLASH) initialization                       */
 251 #define CONFIG_SYS_EBC_PB1AP            0x03050200
 252 #define CONFIG_SYS_EBC_PB1CR            (CONFIG_SYS_FLASH1 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
 253
 254 /* Memory Bank 2 (Flash Bank 2, NOR-FLASH) initialization                       */
 255 #define CONFIG_SYS_EBC_PB2AP            0x03050200
 256 #define CONFIG_SYS_EBC_PB2CR            (CONFIG_SYS_FLASH2 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
 257
 258 /* Memory Bank 3 (Flash Bank 3, NOR-FLASH) initialization                       */
 259 #define CONFIG_SYS_EBC_PB3AP            0x03050200
 260 #define CONFIG_SYS_EBC_PB3CR            (CONFIG_SYS_FLASH3 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
 261
 262 /* Memory Bank 7 (USB controller) initialization                                */
 263 #define CONFIG_SYS_EBC_PB7AP            0x02015000
 264 #define CONFIG_SYS_EBC_PB7CR            (CONFIG_SYS_USB | 0xFE000) /* BAS=0xF00,BS=128MB,BU=R/W,BW=16bit*/
 265
 266 /*-----------------------------------------------------------------------
 267  * FLASH related
 268  *----------------------------------------------------------------------*/
 269 #define CONFIG_SYS_FLASH_CFI                            /* The flash is CFI compatible  */
 270 #define CONFIG_FLASH_CFI_DRIVER                 /* Use common CFI driver        */
 271
 272 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH3, CONFIG_SYS_FLASH2, CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
 273
 274 #define CONFIG_SYS_MAX_FLASH_BANKS      4       /* max number of memory banks           */
 275 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip    */
 276
 277 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 278 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 279
 280 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
 281 #define CONFIG_SYS_FLASH_PROTECTION     1       /* use hardware flash protection        */
 282
 283 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 284 #define CONFIG_SYS_FLASH_QUIET_TEST     1       /* don't warn upon unknown flash        */
 285
 286 #define CONFIG_ENV_IS_IN_FLASH     1    /* use FLASH for environment vars       */
 287
 288 #define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector          */
 289 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
 290 #define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector     */
 291
 292 /* Address and size of Redundant Environment Sector     */
 293 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 294 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 295
 296 /*
 297  * For booting Linux, the board info and command line data
 298  * have to be in the first 8 MB of memory, since this is
 299  * the maximum mapped by the Linux kernel during initialization.
 300  */
 301 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 302
 303 #if defined(CONFIG_CMD_KGDB)
 304 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 305 #endif
 306 #endif  /* __CONFIG_H */