3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * Based on original work by
6 * Roel Loeffen, (C) Copyright 2006 Prodrive B.V.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 /************************************************************************
28 * p3mx.h - configuration for Prodrive P3M750 & P3M7448 boards
33 * are written into include/config.h by the "make xxx_config" command
34 ***********************************************************************/
38 /*-----------------------------------------------------------------------
39 * High Level Configuration Options
40 *----------------------------------------------------------------------*/
41 #define CONFIG_P3Mx /* used for both board versions */
43 #define CONFIG_SYS_TEXT_BASE 0xfff00000
45 #if defined (CONFIG_P3M750)
46 #define CONFIG_750FX /* 750GL/GX/FX */
47 #define CONFIG_HIGH_BATS /* High BATs supported */
48 #define CONFIG_SYS_BOARD_NAME "P3M750"
49 #define CONFIG_SYS_BUS_CLK 100000000
50 #define CONFIG_SYS_TCLK 100000000
51 #elif defined (CONFIG_P3M7448)
53 #define CONFIG_SYS_BOARD_NAME "P3M7448"
54 #define CONFIG_SYS_BUS_CLK 133333333
55 #define CONFIG_SYS_TCLK 133333333
57 #define CONFIG_SYS_GT_DUAL_CPU /* also for JTAG even with one cpu */
59 /* which initialization functions to call for this board */
60 #define CONFIG_SYS_BOARD_ASM_INIT 1
61 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
62 #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */
64 /*-----------------------------------------------------------------------
65 * Base addresses -- Note these are effective addresses where the
66 * actual resources get mapped (not physical addresses)
67 *----------------------------------------------------------------------*/
68 #define CONFIG_SYS_SDRAM_BASE 0x00000000
70 #define CONFIG_SYS_SDRAM1_BASE 0x10000000 /* each 256 MByte */
73 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
74 #if defined (CONFIG_P3M750)
75 #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of flash banks */
76 #define CONFIG_SYS_BOOT_SIZE _8M /* boot flash */
77 #elif defined (CONFIG_P3M7448)
78 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of flash banks */
79 #define CONFIG_SYS_BOOT_SIZE _16M /* boot flash */
81 #define CONFIG_SYS_BOOT_SPACE CONFIG_SYS_FLASH_BASE /* BOOT_CS0 flash 0 */
82 #define CONFIG_SYS_MONITOR_BASE 0xfff00000
83 #define CONFIG_SYS_RESET_ADDRESS 0xfff00100
84 #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
85 #define CONFIG_SYS_MISC_REGION_BASE 0xf0000000
87 #define CONFIG_SYS_DFL_GT_REGS 0xf1000000 /* boot time GT_REGS */
88 #define CONFIG_SYS_GT_REGS 0xf1000000 /* GT Registers are mapped here */
89 #define CONFIG_SYS_INT_SRAM_BASE 0x42000000 /* GT offers 256k internal SRAM */
91 /*-----------------------------------------------------------------------
92 * Initial RAM & stack pointer (placed in internal SRAM)
93 *----------------------------------------------------------------------*/
95 * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS
96 * To an unused memory region. The stack will remain in cache until RAM
99 #undef CONFIG_SYS_INIT_RAM_LOCK
100 #define CONFIG_SYS_INIT_RAM_ADDR 0x42000000
101 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000
102 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
105 /*-----------------------------------------------------------------------
107 *----------------------------------------------------------------------*/
108 #define CONFIG_MPSC /* MV64460 Serial */
109 #define CONFIG_MPSC_PORT 0
110 #define CONFIG_BAUDRATE 115200 /* console baudrate */
111 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
112 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
113 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
115 /*-----------------------------------------------------------------------
117 *----------------------------------------------------------------------*/
118 /* Change the default ethernet port, use this define (options: 0, 1, 2) */
119 #define CONFIG_SYS_ETH_PORT ETH_0
120 #define MV_ETH_DEVS 2
121 #define CONFIG_PHY_RESET 1 /* reset phy upon startup */
122 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
124 /*-----------------------------------------------------------------------
126 *----------------------------------------------------------------------*/
127 #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
128 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
129 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
130 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
131 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
132 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
133 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
134 #define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
135 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
137 #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
138 #if defined (CONFIG_P3M750)
139 #define CONFIG_ENV_SECT_SIZE 0x20000 /* one sector (1 device) */
140 #elif defined (CONFIG_P3M7448)
141 #define CONFIG_ENV_SECT_SIZE 0x40000 /* two sectors (2 devices parallel */
143 #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
144 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
146 /*-----------------------------------------------------------------------
148 *----------------------------------------------------------------------*/
149 #define CONFIG_MV64460_ECC
151 /*-----------------------------------------------------------------------
153 *----------------------------------------------------------------------*/
154 #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed default */
157 #define CONFIG_RTC_M41T11 1
158 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
159 #define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with linux */
161 /*-----------------------------------------------------------------------
163 *----------------------------------------------------------------------*/
164 #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
165 #define PCI_HOST_FORCE 1 /* configure as pci host */
166 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
168 #undef CONFIG_PCI /* include pci support */
170 #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
171 #define CONFIG_PCI_PNP /* do pci plug-and-play */
172 #define CONFIG_PCI_SCAN_SHOW /* show devices on bus */
173 #endif /* CONFIG_PCI */
175 /* PCI MEMORY MAP section */
176 #define CONFIG_SYS_PCI0_MEM_BASE 0x80000000
177 #define CONFIG_SYS_PCI0_MEM_SIZE _128M
178 #define CONFIG_SYS_PCI1_MEM_BASE 0x88000000
179 #define CONFIG_SYS_PCI1_MEM_SIZE _128M
181 #define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE)
182 #define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE)
184 /* PCI I/O MAP section */
185 #define CONFIG_SYS_PCI0_IO_BASE 0xfa000000
186 #define CONFIG_SYS_PCI0_IO_SIZE _16M
187 #define CONFIG_SYS_PCI1_IO_BASE 0xfb000000
188 #define CONFIG_SYS_PCI1_IO_SIZE _16M
190 #define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE)
191 #define CONFIG_SYS_PCI0_IO_SPACE_PCI 0x00000000
192 #define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE)
193 #define CONFIG_SYS_PCI1_IO_SPACE_PCI 0x00000000
195 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS (CONFIG_SYS_PCI0_IO_BASE)
196 #define CONFIG_SYS_PCI_IDSEL 0x30
198 #undef CONFIG_BOOTARGS
199 #define CONFIG_EXTRA_ENV_SETTINGS_COMMON \
201 "nfsargs=setenv bootargs root=/dev/nfs rw " \
202 "nfsroot=${serverip}:${rootpath}\0" \
203 "ramargs=setenv bootargs root=/dev/ram rw\0" \
204 "addip=setenv bootargs ${bootargs} " \
205 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
206 ":${hostname}:${netdev}:off panic=1\0" \
207 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
208 "flash_nfs=run nfsargs addip addtty;" \
209 "bootm ${kernel_addr}\0" \
210 "flash_self=run ramargs addip addtty;" \
211 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
212 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
214 "rootpath=/opt/eldk/ppc_6xx\0" \
215 "u-boot=p3mx/u-boot/u-boot.bin\0" \
216 "load=tftp 100000 ${u-boot}\0" \
217 "update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;" \
218 "cp.b 100000 fff00000 40000;" \
219 "setenv filesize;saveenv\0" \
220 "upd=run load update\0" \
221 "serverip=11.0.0.152\0"
223 #if defined (CONFIG_P3M750)
224 #define CONFIG_EXTRA_ENV_SETTINGS \
225 CONFIG_EXTRA_ENV_SETTINGS_COMMON \
226 "hostname=p3m750\0" \
227 "bootfile=/tftpboot/p3mx/vxWorks.st\0" \
228 "kernel_addr=fc000000\0" \
229 "ramdisk_addr=fc180000\0" \
230 "vxfile=p3m750/vxWorks\0" \
233 "vxtarget=target\0" \
235 "vxargs=setenv bootargs mgi(0,0)host:${vxfile} h=${serverip} " \
236 "e=${ipaddr} u=${vxuser} pw=${vxpass} tn=${vxtarget} " \
238 #elif defined (CONFIG_P3M7448)
239 #define CONFIG_EXTRA_ENV_SETTINGS \
240 CONFIG_EXTRA_ENV_SETTINGS_COMMON \
244 #if defined (CONFIG_P3M750)
245 #define CONFIG_BOOTCOMMAND "tftp;run vxargs;bootvx"
246 #elif defined (CONFIG_P3M7448)
247 #define CONFIG_BOOTCOMMAND " "
250 #define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
255 #define CONFIG_BOOTP_SUBNETMASK
256 #define CONFIG_BOOTP_GATEWAY
257 #define CONFIG_BOOTP_HOSTNAME
258 #define CONFIG_BOOTP_BOOTPATH
259 #define CONFIG_BOOTP_BOOTFILESIZE
262 * Command line configuration.
264 #include <config_cmd_default.h>
266 #define CONFIG_CMD_ASKENV
267 #define CONFIG_CMD_DATE
268 #define CONFIG_CMD_DIAG
269 #define CONFIG_CMD_ELF
270 #define CONFIG_CMD_I2C
271 #define CONFIG_CMD_IRQ
272 #define CONFIG_CMD_MII
273 #define CONFIG_CMD_NET
274 #define CONFIG_CMD_NFS
275 #define CONFIG_CMD_PING
276 #define CONFIG_CMD_REGINFO
277 #define CONFIG_CMD_PCI
278 #define CONFIG_CMD_CACHE
279 #define CONFIG_CMD_SDRAM
282 /*-----------------------------------------------------------------------
283 * Miscellaneous configurable options
284 *----------------------------------------------------------------------*/
285 #define CONFIG_SYS_HUSH_PARSER
286 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
288 #define CONFIG_SYS_LONGHELP /* undef to save memory */
289 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
290 #if defined(CONFIG_CMD_KGDB)
291 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
293 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
295 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
296 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
297 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
299 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
300 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
302 #define CONFIG_SYS_LOAD_ADDR 0x08000000 /* default load address */
304 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
306 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
307 #define CONFIG_LOOPW 1 /* enable loopw command */
308 #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
309 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
310 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
312 /*-----------------------------------------------------------------------
313 * Marvell MV64460 config settings
314 *----------------------------------------------------------------------*/
315 /* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected device width */
316 #if defined (CONFIG_P3M750)
317 #define CONFIG_SYS_BOOT_PAR 0x8FDFF87F /* 16 bit flash, disable burst*/
318 #elif defined (CONFIG_P3M7448)
319 #define CONFIG_SYS_BOOT_PAR 0x8FEFFFFF /* 32 bit flash, burst enabled */
323 * MPP[0] Serial Port 0 TxD TxD OUT Connected to P14 (buffered)
324 * MPP[1] Serial Port 0 RxD RxD IN Connected to P14 (buffered)
326 * MPP[3] Serial Port 1 TxD TxD OUT Connected to P14 (buffered)
327 * MPP[4] PCI Monarch# GPIO IN Connected to P12
328 * MPP[5] Serial Port 1 RxD RxD IN Connected to P14 (buffered)
329 * MPP[6] PMC Carrier Interrupt 0 Int IN Connected to P14
330 * MPP[7] PMC Carrier Interrupt 1 Int IN Connected to P14
331 * MPP[8] Reserved Do not use
332 * MPP[9] Reserved Do not use
333 * MPP[10] Reserved Do not use
334 * MPP[11] Reserved Do not use
335 * MPP[12] Phy 0 Interrupt Int IN
336 * MPP[13] Phy 1 Interrupt Int IN
339 * MPP[16] PCI Interrupt C Int IN Connected to P11
340 * MPP[17] PCI Interrupt D Int IN Connected to P11
341 * MPP[18] Watchdog NMI# GPIO IN Connected to MPP[24]
342 * MPP[19] Watchdog Expired# WDE OUT Connected to rst logic
343 * MPP[20] Watchdog Status WD_STS IN Read back of rst by watchdog
345 * MPP[22] GP LED Green GPIO OUT
346 * MPP[23] GP LED Red GPIO OUT
347 * MPP[24] Watchdog NMI# Int OUT
350 * MPP[27] PCI Interrupt A Int IN Connected to P11
352 * MPP[29] PCI Interrupt B Int IN Connected to P11
353 * MPP[30] Module reset GPIO OUT Board reset
354 * MPP[31] PCI EReady GPIO IN Connected to P12
356 #define CONFIG_SYS_MPP_CONTROL_0 0x00303022
357 #define CONFIG_SYS_MPP_CONTROL_1 0x00000000
358 #define CONFIG_SYS_MPP_CONTROL_2 0x00004000
359 #define CONFIG_SYS_MPP_CONTROL_3 0x00000004
360 #define CONFIG_SYS_GPP_LEVEL_CONTROL 0x280730D0
362 /*----------------------------------------------------------------------
363 * Initial BAT mappings
367 * 1) GUARDED and WRITE_THRU not allowed in IBATS
368 * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
371 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
372 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
373 #define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT)
374 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
377 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
378 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
379 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
380 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
382 /* PCI0, PCI1 in one BAT */
383 #define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
384 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
385 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
386 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
388 /* GT regs, bootrom, all the devices, PCI I/O */
389 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
390 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
391 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
392 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
394 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
395 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
396 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
397 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
399 /* set rest out of range for Linux !!!!!!!!!!! */
401 /* IBAT5 and DBAT5 */
402 #define CONFIG_SYS_IBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
403 #define CONFIG_SYS_IBAT5U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
404 #define CONFIG_SYS_DBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
405 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
407 /* IBAT6 and DBAT6 */
408 #define CONFIG_SYS_IBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
409 #define CONFIG_SYS_IBAT6U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
410 #define CONFIG_SYS_DBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
411 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
413 /* IBAT7 and DBAT7 */
414 #define CONFIG_SYS_IBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
415 #define CONFIG_SYS_IBAT7U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
416 #define CONFIG_SYS_DBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
417 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
420 * For booting Linux, the board info and command line data
421 * have to be in the first 8 MB of memory, since this is
422 * the maximum mapped by the Linux kernel during initialization.
424 #define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
425 #define CONFIG_SYS_VXWORKS_MAC_PTR 0x42010000 /* use some memory in SRAM that's not used!!! */
427 /*-----------------------------------------------------------------------
428 * Cache Configuration
430 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
431 #if defined(CONFIG_CMD_KGDB)
432 #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
435 /*-----------------------------------------------------------------------
436 * L2CR setup -- make sure this is right for your board!
437 * look in include/mpc74xx.h for the defines used here
439 #define CONFIG_SYS_L2
441 #if defined (CONFIG_750CX) || defined (CONFIG_750FX)
444 #define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
445 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
448 #define L2_ENABLE (L2_INIT | L2CR_L2E)
451 #include <../board/Marvell/include/core.h>
454 #endif /* __CONFIG_H */