2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * QorIQ P1 Tower boards configuration file
13 #define CONFIG_SYS_GENERIC_BOARD
14 #define CONFIG_DISPLAY_BOARDINFO
15 #if defined(CONFIG_TWR_P1025)
16 #define CONFIG_BOARDNAME "TWR-P1025"
18 #define CONFIG_PHY_ATHEROS
20 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Conversion of LBC addr */
21 #define CONFIG_SYS_LBC_LCRR 0x80000002 /* LB clock ratio reg */
25 #define CONFIG_RAMBOOT_SDCARD
26 #define CONFIG_SYS_RAMBOOT
27 #define CONFIG_SYS_EXTRA_ENV_RELOC
28 #define CONFIG_SYS_TEXT_BASE 0x11000000
29 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
32 #ifndef CONFIG_SYS_TEXT_BASE
33 #define CONFIG_SYS_TEXT_BASE 0xeff40000
36 #ifndef CONFIG_RESET_VECTOR_ADDRESS
37 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
40 #ifndef CONFIG_SYS_MONITOR_BASE
41 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
44 /* High Level Configuration Options */
50 #define CONFIG_FSL_ELBC
52 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
53 #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
54 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
55 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
56 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
57 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
59 #define CONFIG_FSL_LAW
60 #define CONFIG_TSEC_ENET /* tsec ethernet support */
61 #define CONFIG_ENV_OVERWRITE
63 #define CONFIG_CMD_SATA
64 #define CONFIG_SATA_SIL3114
65 #define CONFIG_SYS_SATA_MAX_DEVICE 2
70 extern unsigned long get_board_sys_clk(unsigned long dummy);
72 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for TWR-P1025 */
74 #define CONFIG_DDR_CLK_FREQ 66666666
76 #define CONFIG_HWCONFIG
78 * These can be toggled for performance analysis, otherwise use default.
80 #define CONFIG_L2_CACHE
83 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
85 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
86 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
87 #define CONFIG_PANIC_HANG /* do not reset board on panic */
89 #define CONFIG_SYS_CCSRBAR 0xffe00000
90 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
93 #define CONFIG_SYS_FSL_DDR3
95 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M
96 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
98 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
99 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
100 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
102 #define CONFIG_NUM_DDR_CONTROLLERS 1
103 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
105 /* Default settings for DDR3 */
106 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
107 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
108 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
109 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
110 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
111 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
113 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
114 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
115 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
116 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
118 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
119 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655a608
120 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
121 #define CONFIG_SYS_DDR_RCW_1 0x00000000
122 #define CONFIG_SYS_DDR_RCW_2 0x00000000
123 #define CONFIG_SYS_DDR_CONTROL 0xc70c0000 /* Type = DDR3 */
124 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
125 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
126 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
128 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
129 #define CONFIG_SYS_DDR_TIMING_0 0x00220004
130 #define CONFIG_SYS_DDR_TIMING_1 0x5c5b6544
131 #define CONFIG_SYS_DDR_TIMING_2 0x0fa880de
132 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
133 #define CONFIG_SYS_DDR_MODE_1 0x80461320
134 #define CONFIG_SYS_DDR_MODE_2 0x00008000
135 #define CONFIG_SYS_DDR_INTERVAL 0x09480000
140 * 0x0000_0000 0x1fff_ffff DDR Up to 512MB cacheable
141 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
142 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
145 * 0xe000_0000 0xe002_0000 SSD1289 128K non-cacheable
146 * 0xec00_0000 0xefff_ffff FLASH Up to 64M non-cacheable
148 * 0xff90_0000 0xff97_ffff L2 SRAM Up to 512K cacheable
149 * 0xffd0_0000 0xffd0_3fff init ram 16K Cacheable
150 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
154 * Local Bus Definitions
156 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
157 #define CONFIG_SYS_FLASH_BASE 0xec000000
159 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
161 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \
164 #define CONFIG_FLASH_OR_PRELIM 0xfc0000b1
166 #define CONFIG_SYS_SSD_BASE 0xe0000000
167 #define CONFIG_SYS_SSD_BASE_PHYS CONFIG_SYS_SSD_BASE
168 #define CONFIG_SSD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_SSD_BASE_PHYS) | \
170 #define CONFIG_SSD_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
171 OR_GPCM_ACS_DIV2 | OR_GPCM_SCY | \
172 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
174 #define CONFIG_SYS_BR2_PRELIM CONFIG_SSD_BR_PRELIM
175 #define CONFIG_SYS_OR2_PRELIM CONFIG_SSD_OR_PRELIM
177 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
178 #define CONFIG_SYS_FLASH_QUIET_TEST
179 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
181 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
183 #undef CONFIG_SYS_FLASH_CHECKSUM
184 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
185 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
187 #define CONFIG_FLASH_CFI_DRIVER
188 #define CONFIG_SYS_FLASH_CFI
189 #define CONFIG_SYS_FLASH_EMPTY_INFO
190 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
192 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
194 #define CONFIG_SYS_INIT_RAM_LOCK
195 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
196 /* Initial L1 address */
197 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
198 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
199 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
200 /* Size of used area in RAM */
201 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
203 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
204 GENERATED_GBL_DATA_SIZE)
205 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
207 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
208 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
210 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
211 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
217 #define CONFIG_CONS_INDEX 1
218 #undef CONFIG_SERIAL_SOFTWARE_FIFO
219 #define CONFIG_SYS_NS16550
220 #define CONFIG_SYS_NS16550_SERIAL
221 #define CONFIG_SYS_NS16550_REG_SIZE 1
222 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
224 #define CONFIG_SYS_BAUDRATE_TABLE \
225 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
227 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
228 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
230 /* Use the HUSH parser */
231 #define CONFIG_SYS_HUSH_PARSER
232 #ifdef CONFIG_SYS_HUSH_PARSER
233 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
237 * Pass open firmware flat tree
239 #define CONFIG_OF_LIBFDT
240 #define CONFIG_OF_BOARD_SETUP
241 #define CONFIG_OF_STDOUT_VIA_ALIAS
243 /* new uImage format support */
245 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
248 #define CONFIG_SYS_I2C
249 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
250 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C spd and slave address */
251 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
252 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
253 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
258 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C spd and slave address */
259 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
260 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
262 #define CONFIG_SYS_I2C_PCA9555_ADDR 0x23
264 /* enable read and write access to EEPROM */
265 #define CONFIG_CMD_EEPROM
266 #define CONFIG_SYS_I2C_MULTI_EEPROMS
267 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
268 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
269 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
272 * eSPI - Enhanced SPI
274 #define CONFIG_HARD_SPI
275 #define CONFIG_FSL_ESPI
277 #if defined(CONFIG_PCI)
280 * Memory space is mapped 1-1, but I/O space must start from 0.
283 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
284 #define CONFIG_SYS_PCIE2_NAME "TWR-ELEV PCIe SLOT"
285 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
286 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
287 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
288 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
289 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
290 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
291 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
292 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
294 /* controller 1, tgtid 1, Base address a000 */
295 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
296 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
297 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
298 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
299 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
300 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
301 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
302 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
303 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
305 #define CONFIG_NET_MULTI
306 #define CONFIG_PCI_PNP /* do pci plug-and-play */
307 #define CONFIG_E1000 /* Defind e1000 pci Ethernet card*/
308 #define CONFIG_CMD_PCI
310 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
311 #define CONFIG_DOS_PARTITION
312 #endif /* CONFIG_PCI */
314 #if defined(CONFIG_TSEC_ENET)
316 #ifndef CONFIG_NET_MULTI
317 #define CONFIG_NET_MULTI
320 #define CONFIG_MII /* MII PHY management */
322 #define CONFIG_TSEC1_NAME "eTSEC1"
324 #undef CONFIG_TSEC2_NAME
326 #define CONFIG_TSEC3_NAME "eTSEC3"
328 #define TSEC1_PHY_ADDR 2
329 #define TSEC2_PHY_ADDR 0
330 #define TSEC3_PHY_ADDR 1
332 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
333 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
334 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
336 #define TSEC1_PHYIDX 0
337 #define TSEC2_PHYIDX 0
338 #define TSEC3_PHYIDX 0
340 #define CONFIG_ETHPRIME "eTSEC1"
342 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
344 #define CONFIG_HAS_ETH0
345 #define CONFIG_HAS_ETH1
346 #undef CONFIG_HAS_ETH2
347 #endif /* CONFIG_TSEC_ENET */
350 /* QE microcode/firmware address */
351 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
352 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000
353 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
354 #endif /* CONFIG_QE */
356 #ifdef CONFIG_TWR_P1025
358 * QE UEC ethernet configuration
360 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
362 #undef CONFIG_UEC_ETH
363 #define CONFIG_PHY_MODE_NEED_CHANGE
365 #define CONFIG_UEC_ETH1 /* ETH1 */
366 #define CONFIG_HAS_ETH0
368 #ifdef CONFIG_UEC_ETH1
369 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
370 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */
371 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */
372 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
373 #define CONFIG_SYS_UEC1_PHY_ADDR 0x18 /* 0x18 for MII */
374 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
375 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
376 #endif /* CONFIG_UEC_ETH1 */
378 #define CONFIG_UEC_ETH5 /* ETH5 */
379 #define CONFIG_HAS_ETH1
381 #ifdef CONFIG_UEC_ETH5
382 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */
383 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE
384 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */
385 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH
386 #define CONFIG_SYS_UEC5_PHY_ADDR 0x19 /* 0x19 for RMII */
387 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
388 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
389 #endif /* CONFIG_UEC_ETH5 */
390 #endif /* CONFIG_TWR-P1025 */
393 * Dynamic MTD Partition support with mtdparts
395 #define CONFIG_MTD_DEVICE
396 #define CONFIG_MTD_PARTITIONS
397 #define CONFIG_CMD_MTDPARTS
398 #define CONFIG_FLASH_CFI_MTD
399 #define MTDIDS_DEFAULT "nor0=ec000000.nor"
400 #define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:256k(vsc7385-firmware)," \
401 "256k(dtb),5632k(kernel),57856k(fs)," \
402 "256k(qe-ucode-firmware),1280k(u-boot)"
407 #ifdef CONFIG_SYS_RAMBOOT
408 #ifdef CONFIG_RAMBOOT_SDCARD
409 #define CONFIG_ENV_IS_IN_MMC
410 #define CONFIG_ENV_SIZE 0x2000
411 #define CONFIG_SYS_MMC_ENV_DEV 0
413 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
414 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
415 #define CONFIG_ENV_SIZE 0x2000
418 #define CONFIG_ENV_IS_IN_FLASH
419 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
420 #define CONFIG_ENV_SIZE 0x2000
421 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
424 #define CONFIG_LOADS_ECHO /* echo on for serial download */
425 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
428 * Command line configuration.
430 #include <config_cmd_default.h>
432 #define CONFIG_CMD_IRQ
433 #define CONFIG_CMD_PING
434 #define CONFIG_CMD_I2C
435 #define CONFIG_CMD_MII
436 #define CONFIG_CMD_ELF
437 #define CONFIG_CMD_REGINFO
442 #define CONFIG_HAS_FSL_DR_USB
444 #if defined(CONFIG_HAS_FSL_DR_USB)
445 #define CONFIG_USB_EHCI
447 #ifdef CONFIG_USB_EHCI
448 #define CONFIG_CMD_USB
449 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
450 #define CONFIG_USB_EHCI_FSL
451 #define CONFIG_USB_STORAGE
458 #define CONFIG_FSL_ESDHC
459 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
460 #define CONFIG_CMD_MMC
461 #define CONFIG_GENERIC_MMC
464 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
465 || defined(CONFIG_FSL_SATA)
466 #define CONFIG_CMD_EXT2
467 #define CONFIG_CMD_FAT
468 #define CONFIG_DOS_PARTITION
471 #undef CONFIG_WATCHDOG /* watchdog disabled */
474 * Miscellaneous configurable options
476 #define CONFIG_SYS_LONGHELP /* undef to save memory */
477 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
478 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
479 #if defined(CONFIG_CMD_KGDB)
480 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
482 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
484 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
485 /* Print Buffer Size */
486 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
487 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
490 * For booting Linux, the board info and command line data
491 * have to be in the first 64 MB of memory, since this is
492 * the maximum mapped by the Linux kernel during initialization.
494 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
495 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
498 * Environment Configuration
500 #define CONFIG_HOSTNAME unknown
501 #define CONFIG_ROOTPATH "/opt/nfsroot"
502 #define CONFIG_BOOTFILE "uImage"
503 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
505 /* default location for tftp and bootm */
506 #define CONFIG_LOADADDR 1000000
508 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
509 #define CONFIG_BOOTARGS /* the boot command will set bootargs */
511 #define CONFIG_BAUDRATE 115200
513 #define CONFIG_EXTRA_ENV_SETTINGS \
515 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
516 "loadaddr=1000000\0" \
517 "bootfile=uImage\0" \
518 "dtbfile=twr-p1025twr.dtb\0" \
519 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
520 "qefirmwarefile=fsl_qe_ucode_1021_10_A.bin\0" \
521 "tftpflash=tftpboot $loadaddr $uboot; " \
522 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
523 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
524 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
525 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
526 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
527 "kernelflash=tftpboot $loadaddr $bootfile; " \
528 "protect off 0xefa80000 +$filesize; " \
529 "erase 0xefa80000 +$filesize; " \
530 "cp.b $loadaddr 0xefa80000 $filesize; " \
531 "protect on 0xefa80000 +$filesize; " \
532 "cmp.b $loadaddr 0xefa80000 $filesize\0" \
533 "dtbflash=tftpboot $loadaddr $dtbfile; " \
534 "protect off 0xefe80000 +$filesize; " \
535 "erase 0xefe80000 +$filesize; " \
536 "cp.b $loadaddr 0xefe80000 $filesize; " \
537 "protect on 0xefe80000 +$filesize; " \
538 "cmp.b $loadaddr 0xefe80000 $filesize\0" \
539 "ramdiskflash=tftpboot $loadaddr $ramdiskfile; " \
540 "protect off 0xeeb80000 +$filesize; " \
541 "erase 0xeeb80000 +$filesize; " \
542 "cp.b $loadaddr 0xeeb80000 $filesize; " \
543 "protect on 0xeeb80000 +$filesize; " \
544 "cmp.b $loadaddr 0xeeb80000 $filesize\0" \
545 "qefirmwareflash=tftpboot $loadaddr $qefirmwarefile; " \
546 "protect off 0xefec0000 +$filesize; " \
547 "erase 0xefec0000 +$filesize; " \
548 "cp.b $loadaddr 0xefec0000 $filesize; " \
549 "protect on 0xefec0000 +$filesize; " \
550 "cmp.b $loadaddr 0xefec0000 $filesize\0" \
551 "consoledev=ttyS0\0" \
552 "ramdiskaddr=2000000\0" \
553 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
556 "norbootaddr=ef080000\0" \
557 "norfdtaddr=ef040000\0" \
558 "ramdisk_size=120000\0" \
559 "usbboot=setenv bootargs root=/dev/sda1 rw rootdelay=5 " \
560 "console=$consoledev,$baudrate $othbootargs ; bootm 0xefa80000 - 0xefe80000"
562 #define CONFIG_NFSBOOTCOMMAND \
563 "setenv bootargs root=/dev/nfs rw " \
564 "nfsroot=$serverip:$rootpath " \
565 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
566 "console=$consoledev,$baudrate $othbootargs;" \
567 "tftp $loadaddr $bootfile&&" \
568 "tftp $fdtaddr $fdtfile&&" \
569 "bootm $loadaddr - $fdtaddr"
571 #define CONFIG_HDBOOT \
572 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
573 "console=$consoledev,$baudrate $othbootargs;" \
575 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
576 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
577 "bootm $loadaddr - $fdtaddr"
579 #define CONFIG_USB_FAT_BOOT \
580 "setenv bootargs root=/dev/ram rw " \
581 "console=$consoledev,$baudrate $othbootargs " \
582 "ramdisk_size=$ramdisk_size;" \
584 "fatload usb 0:2 $loadaddr $bootfile;" \
585 "fatload usb 0:2 $fdtaddr $fdtfile;" \
586 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
587 "bootm $loadaddr $ramdiskaddr $fdtaddr"
589 #define CONFIG_USB_EXT2_BOOT \
590 "setenv bootargs root=/dev/ram rw " \
591 "console=$consoledev,$baudrate $othbootargs " \
592 "ramdisk_size=$ramdisk_size;" \
594 "ext2load usb 0:4 $loadaddr $bootfile;" \
595 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
596 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
597 "bootm $loadaddr $ramdiskaddr $fdtaddr"
599 #define CONFIG_NORBOOT \
600 "setenv bootargs root=/dev/mtdblock3 rw " \
601 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
602 "bootm $norbootaddr - $norfdtaddr"
604 #define CONFIG_RAMBOOTCOMMAND_TFTP \
605 "setenv bootargs root=/dev/ram rw " \
606 "console=$consoledev,$baudrate $othbootargs " \
607 "ramdisk_size=$ramdisk_size;" \
608 "tftp $ramdiskaddr $ramdiskfile;" \
609 "tftp $loadaddr $bootfile;" \
610 "tftp $fdtaddr $fdtfile;" \
611 "bootm $loadaddr $ramdiskaddr $fdtaddr"
613 #define CONFIG_RAMBOOTCOMMAND \
614 "setenv bootargs root=/dev/ram rw " \
615 "console=$consoledev,$baudrate $othbootargs " \
616 "ramdisk_size=$ramdisk_size;" \
617 "bootm 0xefa80000 0xeeb80000 0xefe80000"
619 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
621 #endif /* __CONFIG_H */