1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2013 Freescale Semiconductor, Inc.
7 * QorIQ P1 Tower boards configuration file
12 #if defined(CONFIG_TWR_P1025)
13 #define CONFIG_BOARDNAME "TWR-P1025"
14 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Conversion of LBC addr */
15 #define CONFIG_SYS_LBC_LCRR 0x80000002 /* LB clock ratio reg */
19 #define CONFIG_RAMBOOT_SDCARD
20 #define CONFIG_SYS_RAMBOOT
21 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
24 #ifndef CONFIG_RESET_VECTOR_ADDRESS
25 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
28 #ifndef CONFIG_SYS_MONITOR_BASE
29 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
32 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
33 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
34 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
35 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
36 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
38 #define CONFIG_ENV_OVERWRITE
40 #define CONFIG_SYS_SATA_MAX_DEVICE 2
44 extern unsigned long get_board_sys_clk(unsigned long dummy);
46 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for TWR-P1025 */
48 #define CONFIG_DDR_CLK_FREQ 66666666
50 #define CONFIG_HWCONFIG
52 * These can be toggled for performance analysis, otherwise use default.
54 #define CONFIG_L2_CACHE
57 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
58 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
60 #define CONFIG_SYS_CCSRBAR 0xffe00000
61 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
65 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M
66 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
68 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
69 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
70 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
72 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
74 /* Default settings for DDR3 */
75 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
76 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
77 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
78 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
79 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
80 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
82 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
83 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
84 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
85 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
87 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
88 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655a608
89 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
90 #define CONFIG_SYS_DDR_RCW_1 0x00000000
91 #define CONFIG_SYS_DDR_RCW_2 0x00000000
92 #define CONFIG_SYS_DDR_CONTROL 0xc70c0000 /* Type = DDR3 */
93 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
94 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
95 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
97 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
98 #define CONFIG_SYS_DDR_TIMING_0 0x00220004
99 #define CONFIG_SYS_DDR_TIMING_1 0x5c5b6544
100 #define CONFIG_SYS_DDR_TIMING_2 0x0fa880de
101 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
102 #define CONFIG_SYS_DDR_MODE_1 0x80461320
103 #define CONFIG_SYS_DDR_MODE_2 0x00008000
104 #define CONFIG_SYS_DDR_INTERVAL 0x09480000
109 * 0x0000_0000 0x1fff_ffff DDR Up to 512MB cacheable
110 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
111 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
114 * 0xe000_0000 0xe002_0000 SSD1289 128K non-cacheable
115 * 0xec00_0000 0xefff_ffff FLASH Up to 64M non-cacheable
117 * 0xff90_0000 0xff97_ffff L2 SRAM Up to 512K cacheable
118 * 0xffd0_0000 0xffd0_3fff init ram 16K Cacheable
119 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
123 * Local Bus Definitions
125 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
126 #define CONFIG_SYS_FLASH_BASE 0xec000000
128 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
130 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \
133 #define CONFIG_FLASH_OR_PRELIM 0xfc0000b1
135 #define CONFIG_SYS_SSD_BASE 0xe0000000
136 #define CONFIG_SYS_SSD_BASE_PHYS CONFIG_SYS_SSD_BASE
137 #define CONFIG_SSD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_SSD_BASE_PHYS) | \
139 #define CONFIG_SSD_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
140 OR_GPCM_ACS_DIV2 | OR_GPCM_SCY | \
141 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
143 #define CONFIG_SYS_BR2_PRELIM CONFIG_SSD_BR_PRELIM
144 #define CONFIG_SYS_OR2_PRELIM CONFIG_SSD_OR_PRELIM
146 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
147 #define CONFIG_SYS_FLASH_QUIET_TEST
148 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
150 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
152 #undef CONFIG_SYS_FLASH_CHECKSUM
153 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
154 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
156 #define CONFIG_SYS_FLASH_EMPTY_INFO
158 #define CONFIG_SYS_INIT_RAM_LOCK
159 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
160 /* Initial L1 address */
161 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
162 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
163 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
164 /* Size of used area in RAM */
165 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
167 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
168 GENERATED_GBL_DATA_SIZE)
169 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
171 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
172 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
174 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
175 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
181 #undef CONFIG_SERIAL_SOFTWARE_FIFO
182 #define CONFIG_SYS_NS16550_SERIAL
183 #define CONFIG_SYS_NS16550_REG_SIZE 1
184 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
186 #define CONFIG_SYS_BAUDRATE_TABLE \
187 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
189 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
190 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
193 #define CONFIG_SYS_I2C
194 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
195 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C spd and slave address */
196 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
197 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
198 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
203 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C spd and slave address */
204 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
205 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
207 #define CONFIG_SYS_I2C_PCA9555_ADDR 0x23
209 /* enable read and write access to EEPROM */
210 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
211 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
212 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
214 #if defined(CONFIG_PCI)
217 * Memory space is mapped 1-1, but I/O space must start from 0.
220 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
221 #define CONFIG_SYS_PCIE2_NAME "TWR-ELEV PCIe SLOT"
222 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
223 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
224 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
225 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
226 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
227 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
228 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
229 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
231 /* controller 1, tgtid 1, Base address a000 */
232 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
233 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
234 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
235 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
236 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
237 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
238 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
239 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
240 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
242 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
243 #endif /* CONFIG_PCI */
245 #if defined(CONFIG_TSEC_ENET)
248 #define CONFIG_TSEC1_NAME "eTSEC1"
250 #undef CONFIG_TSEC2_NAME
252 #define CONFIG_TSEC3_NAME "eTSEC3"
254 #define TSEC1_PHY_ADDR 2
255 #define TSEC2_PHY_ADDR 0
256 #define TSEC3_PHY_ADDR 1
258 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
259 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
260 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
262 #define TSEC1_PHYIDX 0
263 #define TSEC2_PHYIDX 0
264 #define TSEC3_PHYIDX 0
266 #define CONFIG_ETHPRIME "eTSEC1"
268 #define CONFIG_HAS_ETH0
269 #define CONFIG_HAS_ETH1
270 #undef CONFIG_HAS_ETH2
271 #endif /* CONFIG_TSEC_ENET */
274 /* QE microcode/firmware address */
275 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000
276 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
277 #endif /* CONFIG_QE */
279 #ifdef CONFIG_TWR_P1025
281 * QE UEC ethernet configuration
283 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
285 #undef CONFIG_UEC_ETH
286 #define CONFIG_PHY_MODE_NEED_CHANGE
288 #define CONFIG_UEC_ETH1 /* ETH1 */
289 #define CONFIG_HAS_ETH0
291 #ifdef CONFIG_UEC_ETH1
292 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
293 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */
294 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */
295 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
296 #define CONFIG_SYS_UEC1_PHY_ADDR 0x18 /* 0x18 for MII */
297 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
298 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
299 #endif /* CONFIG_UEC_ETH1 */
301 #define CONFIG_UEC_ETH5 /* ETH5 */
302 #define CONFIG_HAS_ETH1
304 #ifdef CONFIG_UEC_ETH5
305 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */
306 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE
307 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */
308 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH
309 #define CONFIG_SYS_UEC5_PHY_ADDR 0x19 /* 0x19 for RMII */
310 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
311 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
312 #endif /* CONFIG_UEC_ETH5 */
313 #endif /* CONFIG_TWR-P1025 */
316 * Dynamic MTD Partition support with mtdparts
322 #ifdef CONFIG_SYS_RAMBOOT
323 #ifdef CONFIG_RAMBOOT_SDCARD
324 #define CONFIG_SYS_MMC_ENV_DEV 0
328 #define CONFIG_LOADS_ECHO /* echo on for serial download */
329 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
334 #define CONFIG_HAS_FSL_DR_USB
336 #if defined(CONFIG_HAS_FSL_DR_USB)
337 #ifdef CONFIG_USB_EHCI_HCD
338 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
339 #define CONFIG_USB_EHCI_FSL
344 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
347 #undef CONFIG_WATCHDOG /* watchdog disabled */
350 * Miscellaneous configurable options
352 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
355 * For booting Linux, the board info and command line data
356 * have to be in the first 64 MB of memory, since this is
357 * the maximum mapped by the Linux kernel during initialization.
359 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
360 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
363 * Environment Configuration
365 #define CONFIG_HOSTNAME "unknown"
366 #define CONFIG_ROOTPATH "/opt/nfsroot"
367 #define CONFIG_BOOTFILE "uImage"
368 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
370 /* default location for tftp and bootm */
371 #define CONFIG_LOADADDR 1000000
373 #define CONFIG_EXTRA_ENV_SETTINGS \
375 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
376 "loadaddr=1000000\0" \
377 "bootfile=uImage\0" \
378 "dtbfile=twr-p1025twr.dtb\0" \
379 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
380 "qefirmwarefile=fsl_qe_ucode_1021_10_A.bin\0" \
381 "tftpflash=tftpboot $loadaddr $uboot; " \
382 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
383 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
384 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
385 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
386 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
387 "kernelflash=tftpboot $loadaddr $bootfile; " \
388 "protect off 0xefa80000 +$filesize; " \
389 "erase 0xefa80000 +$filesize; " \
390 "cp.b $loadaddr 0xefa80000 $filesize; " \
391 "protect on 0xefa80000 +$filesize; " \
392 "cmp.b $loadaddr 0xefa80000 $filesize\0" \
393 "dtbflash=tftpboot $loadaddr $dtbfile; " \
394 "protect off 0xefe80000 +$filesize; " \
395 "erase 0xefe80000 +$filesize; " \
396 "cp.b $loadaddr 0xefe80000 $filesize; " \
397 "protect on 0xefe80000 +$filesize; " \
398 "cmp.b $loadaddr 0xefe80000 $filesize\0" \
399 "ramdiskflash=tftpboot $loadaddr $ramdiskfile; " \
400 "protect off 0xeeb80000 +$filesize; " \
401 "erase 0xeeb80000 +$filesize; " \
402 "cp.b $loadaddr 0xeeb80000 $filesize; " \
403 "protect on 0xeeb80000 +$filesize; " \
404 "cmp.b $loadaddr 0xeeb80000 $filesize\0" \
405 "qefirmwareflash=tftpboot $loadaddr $qefirmwarefile; " \
406 "protect off 0xefec0000 +$filesize; " \
407 "erase 0xefec0000 +$filesize; " \
408 "cp.b $loadaddr 0xefec0000 $filesize; " \
409 "protect on 0xefec0000 +$filesize; " \
410 "cmp.b $loadaddr 0xefec0000 $filesize\0" \
411 "consoledev=ttyS0\0" \
412 "ramdiskaddr=2000000\0" \
413 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
414 "fdtaddr=1e00000\0" \
416 "norbootaddr=ef080000\0" \
417 "norfdtaddr=ef040000\0" \
418 "ramdisk_size=120000\0" \
419 "usbboot=setenv bootargs root=/dev/sda1 rw rootdelay=5 " \
420 "console=$consoledev,$baudrate $othbootargs ; bootm 0xefa80000 - 0xefe80000"
422 #define CONFIG_NFSBOOTCOMMAND \
423 "setenv bootargs root=/dev/nfs rw " \
424 "nfsroot=$serverip:$rootpath " \
425 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
426 "console=$consoledev,$baudrate $othbootargs;" \
427 "tftp $loadaddr $bootfile&&" \
428 "tftp $fdtaddr $fdtfile&&" \
429 "bootm $loadaddr - $fdtaddr"
431 #define CONFIG_HDBOOT \
432 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
433 "console=$consoledev,$baudrate $othbootargs;" \
435 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
436 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
437 "bootm $loadaddr - $fdtaddr"
439 #define CONFIG_USB_FAT_BOOT \
440 "setenv bootargs root=/dev/ram rw " \
441 "console=$consoledev,$baudrate $othbootargs " \
442 "ramdisk_size=$ramdisk_size;" \
444 "fatload usb 0:2 $loadaddr $bootfile;" \
445 "fatload usb 0:2 $fdtaddr $fdtfile;" \
446 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
447 "bootm $loadaddr $ramdiskaddr $fdtaddr"
449 #define CONFIG_USB_EXT2_BOOT \
450 "setenv bootargs root=/dev/ram rw " \
451 "console=$consoledev,$baudrate $othbootargs " \
452 "ramdisk_size=$ramdisk_size;" \
454 "ext2load usb 0:4 $loadaddr $bootfile;" \
455 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
456 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
457 "bootm $loadaddr $ramdiskaddr $fdtaddr"
459 #define CONFIG_NORBOOT \
460 "setenv bootargs root=/dev/mtdblock3 rw " \
461 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
462 "bootm $norbootaddr - $norfdtaddr"
464 #define CONFIG_RAMBOOTCOMMAND_TFTP \
465 "setenv bootargs root=/dev/ram rw " \
466 "console=$consoledev,$baudrate $othbootargs " \
467 "ramdisk_size=$ramdisk_size;" \
468 "tftp $ramdiskaddr $ramdiskfile;" \
469 "tftp $loadaddr $bootfile;" \
470 "tftp $fdtaddr $fdtfile;" \
471 "bootm $loadaddr $ramdiskaddr $fdtaddr"
473 #define CONFIG_RAMBOOTCOMMAND \
474 "setenv bootargs root=/dev/ram rw " \
475 "console=$consoledev,$baudrate $othbootargs " \
476 "ramdisk_size=$ramdisk_size;" \
477 "bootm 0xefa80000 0xeeb80000 0xefe80000"
479 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
481 #endif /* __CONFIG_H */